[coreboot-gerrit] Change in coreboot[master]: soc/amd/common: Move Agesa related files
Richard Spiegel (Code Review)
gerrit at coreboot.org
Thu Dec 7 15:36:13 CET 2017
Richard Spiegel has uploaded this change for review. ( https://review.coreboot.org/22772
Change subject: soc/amd/common: Move Agesa related files
......................................................................
soc/amd/common: Move Agesa related files
Move Agesa related files in soc/amd/common under block directory. Folder
soc/amd/common/block subfolders should mimic soc/intel/common/block
subfolders (one subfolder per subject). Header files should go to
soc/amd/common/block/include/amdblocks.
BUG=b:69262110
TEST=Build with no error gardenia and kahlee (no code change, just folder
reorg).
Change-Id: I5d3064625ddf8caaf370aabaf93165c6817f1ca0
Signed-off-by: Richard Spiegel <richard.spiegel at silverbackltd.com>
---
M src/mainboard/amd/gardenia/BiosCallOuts.c
M src/mainboard/amd/gardenia/OemCustomize.c
M src/mainboard/amd/gardenia/bootblock/BiosCallOuts.c
M src/mainboard/amd/gardenia/bootblock/OemCustomize.c
M src/mainboard/amd/gardenia/mainboard.c
M src/mainboard/google/kahlee/BiosCallOuts.c
M src/mainboard/google/kahlee/OemCustomize.c
M src/mainboard/google/kahlee/bootblock/OemCustomize.c
M src/mainboard/google/kahlee/mainboard.c
M src/mainboard/google/kahlee/variants/baseboard/gpio.c
M src/mainboard/google/kahlee/variants/baseboard/include/baseboard/variants.h
M src/mainboard/google/kahlee/variants/kahlee/gpio.c
M src/soc/amd/common/Makefile.inc
R src/soc/amd/common/block/include/amdblocks/BiosCallOuts.h
R src/soc/amd/common/block/include/amdblocks/agesawrapper.h
R src/soc/amd/common/block/include/amdblocks/agesawrapper_call.h
M src/soc/amd/common/block/include/amdblocks/dimm_spd.h
M src/soc/amd/common/block/include/amdblocks/psp.h
A src/soc/amd/common/block/pi/Kconfig
A src/soc/amd/common/block/pi/Makefile.inc
R src/soc/amd/common/block/pi/agesawrapper.c
R src/soc/amd/common/block/pi/amd_late_init.c
R src/soc/amd/common/block/pi/def_callouts.c
R src/soc/amd/common/block/pi/heapmanager.c
M src/soc/amd/stoneyridge/BiosCallOuts.c
M src/soc/amd/stoneyridge/Kconfig
M src/soc/amd/stoneyridge/bootblock/bootblock.c
M src/soc/amd/stoneyridge/chip.c
M src/soc/amd/stoneyridge/early_setup.c
M src/soc/amd/stoneyridge/imc.c
M src/soc/amd/stoneyridge/include/fchec.h
M src/soc/amd/stoneyridge/northbridge.c
M src/soc/amd/stoneyridge/romstage.c
M src/soc/amd/stoneyridge/smbus_spd.c
M src/vendorcode/amd/pi/00670F00/Makefile.inc
35 files changed, 227 insertions(+), 166 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/22772/1
diff --git a/src/mainboard/amd/gardenia/BiosCallOuts.c b/src/mainboard/amd/gardenia/BiosCallOuts.c
index 398fadb..158642a 100644
--- a/src/mainboard/amd/gardenia/BiosCallOuts.c
+++ b/src/mainboard/amd/gardenia/BiosCallOuts.c
@@ -13,8 +13,8 @@
* GNU General Public License for more details.
*/
-#include <agesawrapper.h>
-#include <BiosCallOuts.h>
+#include <amdblocks/agesawrapper.h>
+#include <amdblocks/BiosCallOuts.h>
#include <soc/imc.h>
#include <soc/southbridge.h>
#include <stdlib.h>
diff --git a/src/mainboard/amd/gardenia/OemCustomize.c b/src/mainboard/amd/gardenia/OemCustomize.c
index 8c7a8ac..f4d7769 100644
--- a/src/mainboard/amd/gardenia/OemCustomize.c
+++ b/src/mainboard/amd/gardenia/OemCustomize.c
@@ -14,7 +14,7 @@
*/
#include <chip.h>
-#include <agesawrapper.h>
+#include <amdblocks/agesawrapper.h>
#define DIMMS_PER_CHANNEL 2
#if DIMMS_PER_CHANNEL > MAX_DIMMS_PER_CH
diff --git a/src/mainboard/amd/gardenia/bootblock/BiosCallOuts.c b/src/mainboard/amd/gardenia/bootblock/BiosCallOuts.c
index 6b52162..7e60dae 100644
--- a/src/mainboard/amd/gardenia/bootblock/BiosCallOuts.c
+++ b/src/mainboard/amd/gardenia/bootblock/BiosCallOuts.c
@@ -13,8 +13,8 @@
* GNU General Public License for more details.
*/
-#include <agesawrapper.h>
-#include <BiosCallOuts.h>
+#include <amdblocks/agesawrapper.h>
+#include <amdblocks/BiosCallOuts.h>
#include <soc/southbridge.h>
#include <stdlib.h>
diff --git a/src/mainboard/amd/gardenia/bootblock/OemCustomize.c b/src/mainboard/amd/gardenia/bootblock/OemCustomize.c
index 82b77f2..0d837cc 100644
--- a/src/mainboard/amd/gardenia/bootblock/OemCustomize.c
+++ b/src/mainboard/amd/gardenia/bootblock/OemCustomize.c
@@ -13,7 +13,7 @@
* GNU General Public License for more details.
*/
-#include <agesawrapper.h>
+#include <amdblocks/agesawrapper.h>
#define FILECODE PROC_GNB_PCIE_FAMILY_0X15_F15PCIECOMPLEXCONFIG_FILECODE
diff --git a/src/mainboard/amd/gardenia/mainboard.c b/src/mainboard/amd/gardenia/mainboard.c
index 25cf5b3..8df97fa 100644
--- a/src/mainboard/amd/gardenia/mainboard.c
+++ b/src/mainboard/amd/gardenia/mainboard.c
@@ -16,8 +16,8 @@
#include <console/console.h>
#include <device/device.h>
#include <arch/acpi.h>
-#include <agesawrapper.h>
#include <amdblocks/amd_pci_util.h>
+#include <amdblocks/agesawrapper.h>
/***********************************************************
* These arrays set up the FCH PCI_INTR registers 0xC00/0xC01.
diff --git a/src/mainboard/google/kahlee/BiosCallOuts.c b/src/mainboard/google/kahlee/BiosCallOuts.c
index fd8465a..1c0df4d 100644
--- a/src/mainboard/google/kahlee/BiosCallOuts.c
+++ b/src/mainboard/google/kahlee/BiosCallOuts.c
@@ -13,8 +13,8 @@
* GNU General Public License for more details.
*/
-#include <agesawrapper.h>
-#include <BiosCallOuts.h>
+#include <amdblocks/agesawrapper.h>
+#include <amdblocks/BiosCallOuts.h>
#include <soc/southbridge.h>
#include <stdlib.h>
#include <baseboard/variants.h>
diff --git a/src/mainboard/google/kahlee/OemCustomize.c b/src/mainboard/google/kahlee/OemCustomize.c
index c507526..8ab8e54 100644
--- a/src/mainboard/google/kahlee/OemCustomize.c
+++ b/src/mainboard/google/kahlee/OemCustomize.c
@@ -14,7 +14,7 @@
*/
#include <chip.h>
-#include <agesawrapper.h>
+#include <amdblocks/agesawrapper.h>
#define DIMMS_PER_CHANNEL 1
#if DIMMS_PER_CHANNEL > MAX_DIMMS_PER_CH
diff --git a/src/mainboard/google/kahlee/bootblock/OemCustomize.c b/src/mainboard/google/kahlee/bootblock/OemCustomize.c
index 0551184..997f010 100644
--- a/src/mainboard/google/kahlee/bootblock/OemCustomize.c
+++ b/src/mainboard/google/kahlee/bootblock/OemCustomize.c
@@ -13,7 +13,7 @@
* GNU General Public License for more details.
*/
-#include <agesawrapper.h>
+#include <amdblocks/agesawrapper.h>
static const PCIe_PORT_DESCRIPTOR PortList[] = {
/* Initialize Port descriptor (PCIe port, Lanes 7:4, D2F1) for NC*/
diff --git a/src/mainboard/google/kahlee/mainboard.c b/src/mainboard/google/kahlee/mainboard.c
index fc13567..229cc5a 100644
--- a/src/mainboard/google/kahlee/mainboard.c
+++ b/src/mainboard/google/kahlee/mainboard.c
@@ -16,8 +16,8 @@
#include <console/console.h>
#include <device/device.h>
#include <arch/acpi.h>
-#include <agesawrapper.h>
#include <amdblocks/amd_pci_util.h>
+#include <amdblocks/agesawrapper.h>
#include <cbmem.h>
#include <baseboard/variants.h>
#include <boardid.h>
diff --git a/src/mainboard/google/kahlee/variants/baseboard/gpio.c b/src/mainboard/google/kahlee/variants/baseboard/gpio.c
index 925ece9..86c87bb 100644
--- a/src/mainboard/google/kahlee/variants/baseboard/gpio.c
+++ b/src/mainboard/google/kahlee/variants/baseboard/gpio.c
@@ -13,7 +13,7 @@
* GNU General Public License for more details.
*/
-#include <agesawrapper.h>
+#include <amdblocks/agesawrapper.h>
#include <baseboard/variants.h>
#include <soc/gpio.h>
#include <soc/smi.h>
diff --git a/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/variants.h
index 33054f5..9c54794 100644
--- a/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/variants.h
+++ b/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/variants.h
@@ -19,7 +19,7 @@
#include <stddef.h>
#include <soc/smi.h>
-#include <agesawrapper.h>
+#include <amdblocks/agesawrapper.h>
const GPIO_CONTROL *get_gpio_table(void);
const struct sci_source *get_gpe_table(size_t *num);
diff --git a/src/mainboard/google/kahlee/variants/kahlee/gpio.c b/src/mainboard/google/kahlee/variants/kahlee/gpio.c
index 97b0655..14424b7 100644
--- a/src/mainboard/google/kahlee/variants/kahlee/gpio.c
+++ b/src/mainboard/google/kahlee/variants/kahlee/gpio.c
@@ -13,7 +13,7 @@
* GNU General Public License for more details.
*/
-#include <agesawrapper.h>
+#include <amdblocks/agesawrapper.h>
#include <baseboard/variants.h>
#include <soc/smi.h>
#include <soc/southbridge.h>
diff --git a/src/soc/amd/common/Makefile.inc b/src/soc/amd/common/Makefile.inc
index b485bb3..103c3bf 100644
--- a/src/soc/amd/common/Makefile.inc
+++ b/src/soc/amd/common/Makefile.inc
@@ -2,19 +2,6 @@
CPPFLAGS_common += -I$(src)/soc/amd/common
-bootblock-y += agesawrapper.c
-bootblock-y += def_callouts.c
-bootblock-y += heapmanager.c
-
-romstage-y += agesawrapper.c
-romstage-y += def_callouts.c
-romstage-y += heapmanager.c
-
-ramstage-y += agesawrapper.c
-ramstage-y += amd_late_init.c
-ramstage-y += def_callouts.c
-ramstage-y += heapmanager.c
-
subdirs-$(CONFIG_SOC_AMD_COMMON_BLOCK) += block
endif
diff --git a/src/soc/amd/common/BiosCallOuts.h b/src/soc/amd/common/block/include/amdblocks/BiosCallOuts.h
similarity index 98%
rename from src/soc/amd/common/BiosCallOuts.h
rename to src/soc/amd/common/block/include/amdblocks/BiosCallOuts.h
index 5237d52..2302889 100644
--- a/src/soc/amd/common/BiosCallOuts.h
+++ b/src/soc/amd/common/block/include/amdblocks/BiosCallOuts.h
@@ -17,7 +17,7 @@
#ifndef __CALLOUTS_AMD_AGESA_H__
#define __CALLOUTS_AMD_AGESA_H__
-#include "agesawrapper.h"
+#include <amdblocks/agesawrapper.h>
#define BIOS_HEAP_START_ADDRESS 0x010000000
#define BIOS_HEAP_SIZE 0x30000
diff --git a/src/soc/amd/common/agesawrapper.h b/src/soc/amd/common/block/include/amdblocks/agesawrapper.h
similarity index 100%
rename from src/soc/amd/common/agesawrapper.h
rename to src/soc/amd/common/block/include/amdblocks/agesawrapper.h
diff --git a/src/soc/amd/common/agesawrapper_call.h b/src/soc/amd/common/block/include/amdblocks/agesawrapper_call.h
similarity index 92%
rename from src/soc/amd/common/agesawrapper_call.h
rename to src/soc/amd/common/block/include/amdblocks/agesawrapper_call.h
index 01e2620..ea0206b 100644
--- a/src/soc/amd/common/agesawrapper_call.h
+++ b/src/soc/amd/common/block/include/amdblocks/agesawrapper_call.h
@@ -14,7 +14,7 @@
#ifndef __AGESAWRAPPER_CALL_H__
#define __AGESAWRAPPER_CALL_H__
-#include "agesawrapper.h"
+#include <amdblocks/agesawrapper.h>
#include <stdint.h>
#include <console/console.h>
@@ -32,7 +32,8 @@
*/
static const char *decodeAGESA_STATUS(AGESA_STATUS sret)
{
- const char *statusStrings[] = { "AGESA_SUCCESS", "AGESA_UNSUPPORTED",
+ static const char * const statusStrings[] = {
+ "AGESA_SUCCESS", "AGESA_UNSUPPORTED",
"AGESA_BOUNDS_CHK", "AGESA_ALERT",
"AGESA_WARNING", "AGESA_ERROR",
"AGESA_CRITICAL", "AGESA_FATAL"
diff --git a/src/soc/amd/common/block/include/amdblocks/dimm_spd.h b/src/soc/amd/common/block/include/amdblocks/dimm_spd.h
index e29edc5..60107c9 100644
--- a/src/soc/amd/common/block/include/amdblocks/dimm_spd.h
+++ b/src/soc/amd/common/block/include/amdblocks/dimm_spd.h
@@ -16,7 +16,7 @@
#ifndef __DIMMSPD_H__
#define __DIMMSPD_H__
-#include <agesawrapper.h>
+#include <amdblocks/agesawrapper.h>
#include <stddef.h>
#include <stdint.h>
diff --git a/src/soc/amd/common/block/include/amdblocks/psp.h b/src/soc/amd/common/block/include/amdblocks/psp.h
index 57ba649..4c9878a 100644
--- a/src/soc/amd/common/block/include/amdblocks/psp.h
+++ b/src/soc/amd/common/block/include/amdblocks/psp.h
@@ -16,7 +16,7 @@
#ifndef __AMD_PSP_H__
#define __AMD_PSP_H__
-#include <agesawrapper.h>
+#include <amdblocks/agesawrapper.h>
#include <soc/pci_devs.h>
#include <stdint.h>
#include <compiler.h>
diff --git a/src/soc/amd/common/block/pi/Kconfig b/src/soc/amd/common/block/pi/Kconfig
new file mode 100644
index 0000000..f11d6ed
--- /dev/null
+++ b/src/soc/amd/common/block/pi/Kconfig
@@ -0,0 +1,6 @@
+config SOC_AMD_COMMON_BLOCK_PI
+ bool
+ default n
+ help
+ This option builds functions that interface AMD's AGESA.
+
diff --git a/src/soc/amd/common/block/pi/Makefile.inc b/src/soc/amd/common/block/pi/Makefile.inc
new file mode 100644
index 0000000..de6bf78
--- /dev/null
+++ b/src/soc/amd/common/block/pi/Makefile.inc
@@ -0,0 +1,16 @@
+ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_PI),y)
+
+bootblock-y += agesawrapper.c
+bootblock-y += def_callouts.c
+bootblock-y += heapmanager.c
+
+romstage-y += agesawrapper.c
+romstage-y += def_callouts.c
+romstage-y += heapmanager.c
+
+ramstage-y += agesawrapper.c
+ramstage-y += amd_late_init.c
+ramstage-y += def_callouts.c
+ramstage-y += heapmanager.c
+
+endif
diff --git a/src/soc/amd/common/agesawrapper.c b/src/soc/amd/common/block/pi/agesawrapper.c
similarity index 74%
rename from src/soc/amd/common/agesawrapper.c
rename to src/soc/amd/common/block/pi/agesawrapper.c
index b939183..1c90eb3 100644
--- a/src/soc/amd/common/agesawrapper.c
+++ b/src/soc/amd/common/block/pi/agesawrapper.c
@@ -13,12 +13,12 @@
* GNU General Public License for more details.
*/
-#include "agesawrapper.h"
+#include <amdblocks/agesawrapper.h>
#include <cbfs.h>
#include <cbmem.h>
#include <delay.h>
#include <cpu/x86/mtrr.h>
-#include <BiosCallOuts.h>
+#include <amdblocks/BiosCallOuts.h>
#include <string.h>
void __attribute__((weak)) SetMemParams(AMD_POST_PARAMS *PostParams) {}
@@ -57,13 +57,20 @@
AmdParamStruct.StdHeader.ImageBasePtr = 0;
AmdCreateStruct (&AmdParamStruct);
- AmdResetParams.FchInterface.Xhci0Enable = IS_ENABLED(CONFIG_STONEYRIDGE_XHCI_ENABLE);
+ AmdResetParams.FchInterface.Xhci0Enable =
+ IS_ENABLED(CONFIG_STONEYRIDGE_XHCI_ENABLE);
- AmdResetParams.FchInterface.SataEnable = !((CONFIG_STONEYRIDGE_SATA_MODE == 0) || (CONFIG_STONEYRIDGE_SATA_MODE == 3));
- AmdResetParams.FchInterface.IdeEnable = (CONFIG_STONEYRIDGE_SATA_MODE == 0) || (CONFIG_STONEYRIDGE_SATA_MODE == 3);
+ AmdResetParams.FchInterface.SataEnable =
+ !((CONFIG_STONEYRIDGE_SATA_MODE == 0) ||
+ (CONFIG_STONEYRIDGE_SATA_MODE == 3));
+ AmdResetParams.FchInterface.IdeEnable =
+ (CONFIG_STONEYRIDGE_SATA_MODE == 0) ||
+ (CONFIG_STONEYRIDGE_SATA_MODE == 3);
status = AmdInitReset(&AmdResetParams);
- if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(AmdParamStruct.StdHeader.HeapStatus);
+ if (status != AGESA_SUCCESS)
+ agesawrapper_amdreadeventlog(
+ AmdParamStruct.StdHeader.HeapStatus);
AmdReleaseStruct (&AmdParamStruct);
return status;
}
@@ -90,7 +97,9 @@
AmdEarlyParamsPtr->GnbConfig.PsppPolicy = PsppDisabled;
status = AmdInitEarly ((AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr);
- if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(AmdParamStruct.StdHeader.HeapStatus);
+ if (status != AGESA_SUCCESS)
+ agesawrapper_amdreadeventlog(
+ AmdParamStruct.StdHeader.HeapStatus);
AmdReleaseStruct (&AmdParamStruct);
return status;
@@ -132,34 +141,42 @@
/* If UMA is enabled we currently have it below TOP_MEM as well.
* UMA may or may not be cacheable, so Sub4GCacheTop could be
* higher than UmaBase. With UMA_NONE we see UmaBase==0. */
- if (PostParams->MemConfig.UmaBase)
- backup_top_of_low_cacheable(PostParams->MemConfig.UmaBase << 16);
- else
- backup_top_of_low_cacheable(PostParams->MemConfig.Sub4GCacheTop);
-
+ if (PostParams->MemConfig.UmaBase) {
+ backup_top_of_low_cacheable(PostParams->MemConfig.
+ UmaBase << 16);
+ } else {
+ backup_top_of_low_cacheable(PostParams->MemConfig.
+ Sub4GCacheTop);
+ }
printk(
BIOS_SPEW,
"setup_uma_memory: umamode %s\n",
- (PostParams->MemConfig.UmaMode == UMA_AUTO) ? "UMA_AUTO" :
- (PostParams->MemConfig.UmaMode == UMA_SPECIFIED) ? "UMA_SPECIFIED" :
- (PostParams->MemConfig.UmaMode == UMA_NONE) ? "UMA_NONE" :
- "unknown"
+ (PostParams->MemConfig.UmaMode == UMA_AUTO) ?
+ "UMA_AUTO" :
+ (PostParams->MemConfig.UmaMode == UMA_SPECIFIED) ?
+ "UMA_SPECIFIED" :
+ (PostParams->MemConfig.UmaMode == UMA_NONE) ?
+ "UMA_NONE" : "unknown"
);
printk(
BIOS_SPEW,
- "setup_uma_memory: syslimit 0x%08llX, bottomio 0x%08lx\n",
- (unsigned long long)(PostParams->MemConfig.SysLimit) << 16,
+ "setup_uma_memory: syslimit 0x%08llX,"
+ " bottomio 0x%08lx\n",
+ (unsigned long long)(PostParams->
+ MemConfig.SysLimit) << 16,
(unsigned long)(PostParams->MemConfig.BottomIo) << 16
);
printk(
BIOS_SPEW,
"setup_uma_memory: uma size %luMB, uma start 0x%08lx\n",
- (unsigned long)(PostParams->MemConfig.UmaSize) >> (20 - 16),
+ (unsigned long)(PostParams->MemConfig.UmaSize) >>
+ (20 - 16),
(unsigned long)(PostParams->MemConfig.UmaBase) << 16
);
- if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(PostParams->StdHeader.HeapStatus);
+ if (status != AGESA_SUCCESS)
+ agesawrapper_amdreadeventlog(PostParams->StdHeader.HeapStatus);
AmdReleaseStruct (&AmdParamStruct);
return status;
@@ -184,13 +201,19 @@
EnvParam->FchInterface.AzaliaController = AzEnable;
EnvParam->FchInterface.SataClass = CONFIG_STONEYRIDGE_SATA_MODE;
- EnvParam->FchInterface.SataEnable = !((CONFIG_STONEYRIDGE_SATA_MODE == 0) || (CONFIG_STONEYRIDGE_SATA_MODE == 3));
- EnvParam->FchInterface.IdeEnable = (CONFIG_STONEYRIDGE_SATA_MODE == 0) || (CONFIG_STONEYRIDGE_SATA_MODE == 3);
- EnvParam->FchInterface.SataIdeMode = (CONFIG_STONEYRIDGE_SATA_MODE == 3);
+ EnvParam->FchInterface.SataEnable =
+ !((CONFIG_STONEYRIDGE_SATA_MODE == 0) ||
+ (CONFIG_STONEYRIDGE_SATA_MODE == 3));
+ EnvParam->FchInterface.IdeEnable =
+ (CONFIG_STONEYRIDGE_SATA_MODE == 0) ||
+ (CONFIG_STONEYRIDGE_SATA_MODE == 3);
+ EnvParam->FchInterface.SataIdeMode =
+ (CONFIG_STONEYRIDGE_SATA_MODE == 3);
EnvParam->GnbEnvConfiguration.IommuSupport = FALSE;
status = AmdInitEnv (EnvParam);
- if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(EnvParam->StdHeader.HeapStatus);
+ if (status != AGESA_SUCCESS)
+ agesawrapper_amdreadeventlog(EnvParam->StdHeader.HeapStatus);
/* Initialize Subordinate Bus Number and Secondary Bus Number
* In platform BIOS this address is allocated by PCI enumeration code
Modify D1F0x18
@@ -200,7 +223,7 @@
}
#ifndef __PRE_RAM__
-VOID* agesawrapper_getlateinitptr (int pick)
+VOID *agesawrapper_getlateinitptr (int pick)
{
switch (pick) {
case PICK_DMI:
@@ -248,17 +271,26 @@
AmdCreateStruct (&AmdParamStruct);
MidParam = (AMD_MID_PARAMS *)AmdParamStruct.NewStructPtr;
- MidParam->GnbMidConfiguration.iGpuVgaMode = 0;/* 0 iGpuVgaAdapter, 1 iGpuVgaNonAdapter; */
+ /* 0 iGpuVgaAdapter, 1 iGpuVgaNonAdapter; */
+ MidParam->GnbMidConfiguration.iGpuVgaMode = 0;
+
MidParam->GnbMidConfiguration.GnbIoapicAddress = 0xFEC20000;
MidParam->FchInterface.AzaliaController = AzEnable;
MidParam->FchInterface.SataClass = CONFIG_STONEYRIDGE_SATA_MODE;
- MidParam->FchInterface.SataEnable = !((CONFIG_STONEYRIDGE_SATA_MODE == 0) || (CONFIG_STONEYRIDGE_SATA_MODE == 3));
- MidParam->FchInterface.IdeEnable = (CONFIG_STONEYRIDGE_SATA_MODE == 0) || (CONFIG_STONEYRIDGE_SATA_MODE == 3);
- MidParam->FchInterface.SataIdeMode = (CONFIG_STONEYRIDGE_SATA_MODE == 3);
+ MidParam->FchInterface.SataEnable =
+ !((CONFIG_STONEYRIDGE_SATA_MODE == 0) ||
+ (CONFIG_STONEYRIDGE_SATA_MODE == 3));
+ MidParam->FchInterface.IdeEnable =
+ (CONFIG_STONEYRIDGE_SATA_MODE == 0) ||
+ (CONFIG_STONEYRIDGE_SATA_MODE == 3);
+ MidParam->FchInterface.SataIdeMode =
+ (CONFIG_STONEYRIDGE_SATA_MODE == 3);
status = AmdInitMid ((AMD_MID_PARAMS *)AmdParamStruct.NewStructPtr);
- if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(AmdParamStruct.StdHeader.HeapStatus);
+ if (status != AGESA_SUCCESS)
+ agesawrapper_amdreadeventlog(
+ AmdParamStruct.StdHeader.HeapStatus);
AmdReleaseStruct (&AmdParamStruct);
return status;
@@ -281,12 +313,16 @@
AmdParamStruct.StdHeader.Func = 0;
AmdParamStruct.StdHeader.ImageBasePtr = 0;
- /* NOTE: if not call amdcreatestruct, the initializer(AmdInitLateInitializer) would not be called */
+ /*
+ * NOTE: if not call amdcreatestruct, the initializer
+ * (AmdInitLateInitializer) would not be called
+ */
AmdCreateStruct(&AmdParamStruct);
AmdLateParams = (AMD_LATE_PARAMS *)AmdParamStruct.NewStructPtr;
Status = AmdInitLate(AmdLateParams);
if (Status != AGESA_SUCCESS) {
- agesawrapper_amdreadeventlog(AmdLateParams->StdHeader.HeapStatus);
+ agesawrapper_amdreadeventlog(
+ AmdLateParams->StdHeader.HeapStatus);
ASSERT(Status == AGESA_SUCCESS);
}
@@ -302,8 +338,9 @@
printk(BIOS_DEBUG, "DmiTable:%x, AcpiPstatein: %x, AcpiSrat:%x,"
"AcpiSlit:%x, Mce:%x, Cmc:%x,"
"Alib:%x, AcpiIvrs:%x in %s\n",
- (unsigned int)DmiTable, (unsigned int)AcpiPstate, (unsigned int)AcpiSrat,
- (unsigned int)AcpiSlit, (unsigned int)AcpiWheaMce, (unsigned int)AcpiWheaCmc,
+ (unsigned int)DmiTable, (unsigned int)AcpiPstate,
+ (unsigned int)AcpiSrat, (unsigned int)AcpiSlit,
+ (unsigned int)AcpiWheaMce, (unsigned int)AcpiWheaCmc,
(unsigned int)AcpiAlib, (unsigned int)AcpiIvrs, __func__);
/* AmdReleaseStruct (&AmdParamStruct); */
@@ -352,9 +389,16 @@
AmdEventParams.StdHeader.HeapStatus = HeapStatus;
Status = AmdReadEventLog (&AmdEventParams);
while (AmdEventParams.EventClass != 0) {
- printk(BIOS_DEBUG,"\nEventLog: EventClass = %x, EventInfo = %x.\n", (unsigned int)AmdEventParams.EventClass,(unsigned int)AmdEventParams.EventInfo);
- printk(BIOS_DEBUG," Param1 = %x, Param2 = %x.\n",(unsigned int)AmdEventParams.DataParam1, (unsigned int)AmdEventParams.DataParam2);
- printk(BIOS_DEBUG," Param3 = %x, Param4 = %x.\n",(unsigned int)AmdEventParams.DataParam3, (unsigned int)AmdEventParams.DataParam4);
+ printk(BIOS_DEBUG,
+ "\nEventLog: EventClass = %x, EventInfo = %x.\n",
+ (unsigned int)AmdEventParams.EventClass,
+ (unsigned int)AmdEventParams.EventInfo);
+ printk(BIOS_DEBUG," Param1 = %x, Param2 = %x.\n",
+ (unsigned int)AmdEventParams.DataParam1,
+ (unsigned int)AmdEventParams.DataParam2);
+ printk(BIOS_DEBUG," Param3 = %x, Param4 = %x.\n",
+ (unsigned int)AmdEventParams.DataParam3,
+ (unsigned int)AmdEventParams.DataParam4);
Status = AmdReadEventLog (&AmdEventParams);
}
@@ -363,9 +407,9 @@
const void *agesawrapper_locate_module (const CHAR8 name[8])
{
- const void* agesa;
- const AMD_IMAGE_HEADER* image;
- const AMD_MODULE_HEADER* module;
+ const void *agesa;
+ const AMD_IMAGE_HEADER *image;
+ const AMD_MODULE_HEADER *module;
size_t file_size;
agesa = cbfs_boot_map_with_leak((const char *)CONFIG_AGESA_CBFS_NAME,
@@ -374,7 +418,7 @@
if (!agesa)
return NULL;
image = LibAmdLocateImage(agesa, agesa + file_size - 1, 4096, name);
- module = (AMD_MODULE_HEADER*)image->ModuleInfoOffset;
+ module = (AMD_MODULE_HEADER *)image->ModuleInfoOffset;
return module;
}
diff --git a/src/soc/amd/common/amd_late_init.c b/src/soc/amd/common/block/pi/amd_late_init.c
similarity index 92%
rename from src/soc/amd/common/amd_late_init.c
rename to src/soc/amd/common/block/pi/amd_late_init.c
index 3aee23c..65667b9 100644
--- a/src/soc/amd/common/amd_late_init.c
+++ b/src/soc/amd/common/block/pi/amd_late_init.c
@@ -20,8 +20,8 @@
#include <device/pci_def.h>
#include <device/pci_ops.h>
-#include <agesawrapper.h>
-#include <agesawrapper_call.h>
+#include <amdblocks/agesawrapper.h>
+#include <amdblocks/agesawrapper_call.h>
static void agesawrapper_post_device(void *unused)
{
diff --git a/src/soc/amd/common/def_callouts.c b/src/soc/amd/common/block/pi/def_callouts.c
similarity index 98%
rename from src/soc/amd/common/def_callouts.c
rename to src/soc/amd/common/block/pi/def_callouts.c
index cc7f556..c05d4de 100644
--- a/src/soc/amd/common/def_callouts.c
+++ b/src/soc/amd/common/block/pi/def_callouts.c
@@ -19,9 +19,9 @@
#include <cpu/x86/mp.h>
#include <timer.h>
#include <amdlib.h>
-#include <BiosCallOuts.h>
-#include "agesawrapper.h"
-#include <agesawrapper_call.h>
+#include <amdblocks/BiosCallOuts.h>
+#include <amdblocks/agesawrapper.h>
+#include <amdblocks/agesawrapper_call.h>
#include <reset.h>
#include <soc/southbridge.h>
diff --git a/src/soc/amd/common/heapmanager.c b/src/soc/amd/common/block/pi/heapmanager.c
similarity index 78%
rename from src/soc/amd/common/heapmanager.c
rename to src/soc/amd/common/block/pi/heapmanager.c
index b991514..a7d7e90 100644
--- a/src/soc/amd/common/heapmanager.c
+++ b/src/soc/amd/common/block/pi/heapmanager.c
@@ -12,10 +12,10 @@
*/
-#include "agesawrapper.h"
+#include <amdblocks/agesawrapper.h>
#include <amdlib.h>
#include <arch/acpi.h>
-#include <BiosCallOuts.h>
+#include <amdblocks/BiosCallOuts.h>
#include <cbmem.h>
#include <string.h>
@@ -113,17 +113,31 @@
while (FreedNodeOffset != 0) { /* todo: simplify this */
FreedNodePtr = (BIOS_BUFFER_NODE *)(BiosHeapBaseAddr
+ FreedNodeOffset);
- if (FreedNodePtr->BufferSize >= (AllocParams->BufferLength + sizeof(BIOS_BUFFER_NODE))) {
+ if (FreedNodePtr->BufferSize >=
+ (AllocParams->BufferLength +
+ sizeof(BIOS_BUFFER_NODE))) {
if (BestFitNodeOffset == 0) {
- /* First node that fits the requested buffer size */
+ /*
+ * First node that fits the requested
+ * buffer size
+ */
BestFitNodeOffset = FreedNodeOffset;
BestFitPrevNodeOffset = PrevNodeOffset;
} else {
- /* Find out whether current node is a better fit than the previous nodes */
- BestFitNodePtr = (BIOS_BUFFER_NODE *)(BiosHeapBaseAddr + BestFitNodeOffset);
- if (BestFitNodePtr->BufferSize > FreedNodePtr->BufferSize) {
- BestFitNodeOffset = FreedNodeOffset;
- BestFitPrevNodeOffset = PrevNodeOffset;
+ /*
+ * Find out whether current node is a
+ * betterfit than the previous nodes
+ */
+ BestFitNodePtr =(BIOS_BUFFER_NODE *)
+ (BiosHeapBaseAddr +
+ BestFitNodeOffset);
+ if (BestFitNodePtr->BufferSize >
+ FreedNodePtr->BufferSize) {
+
+ BestFitNodeOffset =
+ FreedNodeOffset;
+ BestFitPrevNodeOffset =
+ PrevNodeOffset;
}
}
}
@@ -131,66 +145,60 @@
FreedNodeOffset = FreedNodePtr->NextNodeOffset;
} /* end of while loop */
- if (BestFitNodeOffset == 0) {
- /* If we could not find a node that fits the requested
+ if (BestFitNodeOffset == 0)
+ /*
+ * If we could not find a node that fits the requested
* buffer size, return AGESA_BOUNDS_CHK.
*/
return AGESA_BOUNDS_CHK;
+
+ BestFitNodePtr = (BIOS_BUFFER_NODE *)(BiosHeapBaseAddr
+ + BestFitNodeOffset);
+ BestFitPrevNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr +
+ BestFitPrevNodeOffset);
+
+ /*
+ * If BestFitNode is larger than the requested buffer,
+ * fragment the node further
+ */
+ if (BestFitNodePtr->BufferSize > (AllocParams->BufferLength +
+ sizeof(BIOS_BUFFER_NODE))) {
+ NextFreeOffset = BestFitNodeOffset +
+ AllocParams->BufferLength +
+ sizeof(BIOS_BUFFER_NODE);
+ NextFreePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr +
+ NextFreeOffset);
+ NextFreePtr->BufferSize = BestFitNodePtr->BufferSize -
+ (AllocParams->BufferLength +
+ sizeof(BIOS_BUFFER_NODE));
+ NextFreePtr->NextNodeOffset =
+ BestFitNodePtr->NextNodeOffset;
} else {
- BestFitNodePtr = (BIOS_BUFFER_NODE *)(BiosHeapBaseAddr
- + BestFitNodeOffset);
- BestFitPrevNodePtr = (BIOS_BUFFER_NODE *)
- (BiosHeapBaseAddr
- + BestFitPrevNodeOffset);
-
- /* If BestFitNode is larger than the requested buffer,
- * fragment the node further
+ /*
+ * Otherwise, next free node is
+ * NextNodeOffset of BestFitNode
*/
- if (BestFitNodePtr->BufferSize >
- (AllocParams->BufferLength
- + sizeof(BIOS_BUFFER_NODE))) {
- NextFreeOffset = BestFitNodeOffset
- + AllocParams->BufferLength
- + sizeof(BIOS_BUFFER_NODE);
-
- NextFreePtr = (BIOS_BUFFER_NODE *)
- (BiosHeapBaseAddr
- + NextFreeOffset);
- NextFreePtr->BufferSize =
- BestFitNodePtr->BufferSize
- - (AllocParams->BufferLength
- + sizeof(BIOS_BUFFER_NODE));
- NextFreePtr->NextNodeOffset =
- BestFitNodePtr->NextNodeOffset;
- } else {
- /* Otherwise, next free node is
- * NextNodeOffset of BestFitNode
- */
- NextFreeOffset = BestFitNodePtr->NextNodeOffset;
- }
-
- /* If BestFitNode is the first buffer in the list, then
- * update StartOfFreedNodes to reflect new free node.
- */
- if (BestFitNodeOffset ==
- BiosHeapBasePtr->StartOfFreedNodes)
- BiosHeapBasePtr->StartOfFreedNodes =
- NextFreeOffset;
- else
- BestFitPrevNodePtr->NextNodeOffset =
- NextFreeOffset;
-
- /* Add BestFitNode to the list of Allocated nodes */
- CurrNodePtr->NextNodeOffset = BestFitNodeOffset;
- BestFitNodePtr->BufferSize = AllocParams->BufferLength;
- BestFitNodePtr->BufferHandle =
- AllocParams->BufferHandle;
- BestFitNodePtr->NextNodeOffset = 0;
-
- /* Remove BestFitNode from list of Freed nodes */
- AllocParams->BufferPointer = (UINT8 *)BestFitNodePtr
- + sizeof(BIOS_BUFFER_NODE);
+ NextFreeOffset = BestFitNodePtr->NextNodeOffset;
}
+
+ /*
+ * If BestFitNode is the first buffer in the list, then
+ * update StartOfFreedNodes to reflect new free node.
+ */
+ if (BestFitNodeOffset == BiosHeapBasePtr->StartOfFreedNodes)
+ BiosHeapBasePtr->StartOfFreedNodes = NextFreeOffset;
+ else
+ BestFitPrevNodePtr->NextNodeOffset = NextFreeOffset;
+
+ /* Add BestFitNode to the list of Allocated nodes */
+ CurrNodePtr->NextNodeOffset = BestFitNodeOffset;
+ BestFitNodePtr->BufferSize = AllocParams->BufferLength;
+ BestFitNodePtr->BufferHandle = AllocParams->BufferHandle;
+ BestFitNodePtr->NextNodeOffset = 0;
+
+ /* Remove BestFitNode from list of Freed nodes */
+ AllocParams->BufferPointer = (UINT8 *)BestFitNodePtr +
+ sizeof(BIOS_BUFFER_NODE);
}
return AGESA_SUCCESS;
@@ -302,11 +310,10 @@
NextNodePtr->BufferSize = 0;
NextNodePtr->NextNodeOffset = 0;
} else {
- /*AllocNodePtr->NextNodeOffset =
- * FreedNodePtr->NextNodeOffset; */
AllocNodePtr->NextNodeOffset = NextNodeOffset;
}
- /* If deallocated node is adjacent to the previous node,
+ /*
+ * If deallocated node is adjacent to the previous node,
* concatenate both nodes.
*/
PrevNodePtr = (BIOS_BUFFER_NODE *)(BiosHeapBaseAddr
@@ -347,11 +354,10 @@
AllocParams->BufferPointer = NULL;
AllocParams->BufferLength = 0;
return AGESA_BOUNDS_CHK;
- } else {
- AllocNodeOffset = AllocNodePtr->NextNodeOffset;
- AllocNodePtr = (BIOS_BUFFER_NODE *)(BiosHeapBaseAddr
- + AllocNodeOffset);
}
+ AllocNodeOffset = AllocNodePtr->NextNodeOffset;
+ AllocNodePtr = (BIOS_BUFFER_NODE *)(BiosHeapBaseAddr +
+ AllocNodeOffset);
}
AllocParams->BufferPointer = (UINT8 *)((UINT8 *)AllocNodePtr
diff --git a/src/soc/amd/stoneyridge/BiosCallOuts.c b/src/soc/amd/stoneyridge/BiosCallOuts.c
index 87eccaa..f6ac187 100644
--- a/src/soc/amd/stoneyridge/BiosCallOuts.c
+++ b/src/soc/amd/stoneyridge/BiosCallOuts.c
@@ -17,12 +17,12 @@
#include <device/device.h>
#include <device/pci_def.h>
-#include <BiosCallOuts.h>
+#include <amdblocks/BiosCallOuts.h>
#include <soc/southbridge.h>
#include <soc/pci_devs.h>
#include <stdlib.h>
-#include <agesawrapper.h>
+#include <amdblocks/agesawrapper.h>
#include <amdlib.h>
#include <amdblocks/dimm_spd.h>
#include "chip.h"
diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig
index fe4e4ef..4e2fde6 100644
--- a/src/soc/amd/stoneyridge/Kconfig
+++ b/src/soc/amd/stoneyridge/Kconfig
@@ -46,9 +46,10 @@
select SOC_AMD_PI
select SOC_AMD_COMMON
select SOC_AMD_COMMON_BLOCK
- select SOC_AMD_COMMON_BLOCK_PCI
- select SOC_AMD_COMMON_BLOCK_PSP
select SOC_AMD_COMMON_BLOCK_CAR
+ select SOC_AMD_COMMON_BLOCK_PCI
+ select SOC_AMD_COMMON_BLOCK_PI
+ select SOC_AMD_COMMON_BLOCK_PSP
select SOC_AMD_COMMON_BLOCK_SPI
select C_ENVIRONMENT_BOOTBLOCK
select BOOTBLOCK_CONSOLE
diff --git a/src/soc/amd/stoneyridge/bootblock/bootblock.c b/src/soc/amd/stoneyridge/bootblock/bootblock.c
index abe06fb..030c990 100644
--- a/src/soc/amd/stoneyridge/bootblock/bootblock.c
+++ b/src/soc/amd/stoneyridge/bootblock/bootblock.c
@@ -22,8 +22,8 @@
#include <cpu/amd/amdfam15.h>
#include <smp/node.h>
#include <bootblock_common.h>
-#include <agesawrapper.h>
-#include <agesawrapper_call.h>
+#include <amdblocks/agesawrapper.h>
+#include <amdblocks/agesawrapper_call.h>
#include <soc/pci_devs.h>
#include <soc/northbridge.h>
#include <soc/southbridge.h>
diff --git a/src/soc/amd/stoneyridge/chip.c b/src/soc/amd/stoneyridge/chip.c
index 8e4ab2e..8d6a8e4 100644
--- a/src/soc/amd/stoneyridge/chip.c
+++ b/src/soc/amd/stoneyridge/chip.c
@@ -24,8 +24,8 @@
#include <soc/northbridge.h>
#include <soc/southbridge.h>
#include <amdblocks/psp.h>
-#include <agesawrapper.h>
-#include <agesawrapper_call.h>
+#include <amdblocks/agesawrapper.h>
+#include <amdblocks/agesawrapper_call.h>
struct device_operations cpu_bus_ops = {
.read_resources = DEVICE_NOOP,
diff --git a/src/soc/amd/stoneyridge/early_setup.c b/src/soc/amd/stoneyridge/early_setup.c
index 09eb8b6..5bf32f8 100644
--- a/src/soc/amd/stoneyridge/early_setup.c
+++ b/src/soc/amd/stoneyridge/early_setup.c
@@ -13,7 +13,7 @@
* GNU General Public License for more details.
*/
-#include <agesawrapper.h>
+#include <amdblocks/agesawrapper.h>
#include <assert.h>
#include <stdint.h>
#include <arch/io.h>
diff --git a/src/soc/amd/stoneyridge/imc.c b/src/soc/amd/stoneyridge/imc.c
index f7eed20..5d883d9 100644
--- a/src/soc/amd/stoneyridge/imc.c
+++ b/src/soc/amd/stoneyridge/imc.c
@@ -15,7 +15,7 @@
#define __SIMPLE_DEVICE__
-#include <agesawrapper.h>
+#include <amdblocks/agesawrapper.h>
#include <soc/imc.h>
#include <arch/io.h>
#include <device/device.h>
diff --git a/src/soc/amd/stoneyridge/include/fchec.h b/src/soc/amd/stoneyridge/include/fchec.h
index e5e9cfd..80125ec 100644
--- a/src/soc/amd/stoneyridge/include/fchec.h
+++ b/src/soc/amd/stoneyridge/include/fchec.h
@@ -16,7 +16,7 @@
#ifndef __AMD_STONEY_FCHEC__
#define __AMD_STONEY_FCHEC__
-#include <agesawrapper.h>
+#include <amdblocks/agesawrapper.h>
#include <soc/imc.h>
void agesawrapper_fchecfancontrolservice(void);
diff --git a/src/soc/amd/stoneyridge/northbridge.c b/src/soc/amd/stoneyridge/northbridge.c
index 3eb8e8d..27b5388 100644
--- a/src/soc/amd/stoneyridge/northbridge.c
+++ b/src/soc/amd/stoneyridge/northbridge.c
@@ -28,8 +28,8 @@
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ids.h>
-#include <agesawrapper.h>
-#include <agesawrapper_call.h>
+#include <amdblocks/agesawrapper.h>
+#include <amdblocks/agesawrapper_call.h>
#include <soc/northbridge.h>
#include <soc/southbridge.h>
#include <soc/pci_devs.h>
diff --git a/src/soc/amd/stoneyridge/romstage.c b/src/soc/amd/stoneyridge/romstage.c
index 32dee5a..7c738ad 100644
--- a/src/soc/amd/stoneyridge/romstage.c
+++ b/src/soc/amd/stoneyridge/romstage.c
@@ -24,8 +24,8 @@
#include <device/device.h>
#include <chip.h>
#include <program_loading.h>
-#include <agesawrapper.h>
-#include <agesawrapper_call.h>
+#include <amdblocks/agesawrapper.h>
+#include <amdblocks/agesawrapper_call.h>
#include <soc/northbridge.h>
#include <soc/southbridge.h>
#include <amdblocks/psp.h>
diff --git a/src/soc/amd/stoneyridge/smbus_spd.c b/src/soc/amd/stoneyridge/smbus_spd.c
index acd907e..6027400 100644
--- a/src/soc/amd/stoneyridge/smbus_spd.c
+++ b/src/soc/amd/stoneyridge/smbus_spd.c
@@ -13,7 +13,7 @@
* GNU General Public License for more details.
*/
-#include <agesawrapper.h>
+#include <amdblocks/agesawrapper.h>
#include <device/pci_def.h>
#include <device/device.h>
#include <soc/southbridge.h>
diff --git a/src/vendorcode/amd/pi/00670F00/Makefile.inc b/src/vendorcode/amd/pi/00670F00/Makefile.inc
index d59b553..bf04e50 100644
--- a/src/vendorcode/amd/pi/00670F00/Makefile.inc
+++ b/src/vendorcode/amd/pi/00670F00/Makefile.inc
@@ -50,7 +50,7 @@
AGESA_INC += $(BINARY_PI_INC)
AGESA_INC += -I$(src)/soc/amd/stoneyridge/include
-AGESA_INC += -I$(src)/soc/amd/common
+AGESA_INC += -I$(src)/soc/amd/common/block/include/amdblocks
AGESA_INC += -I$(src)/arch/x86/include
AGESA_INC += -I$(src)/include
--
To view, visit https://review.coreboot.org/22772
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I5d3064625ddf8caaf370aabaf93165c6817f1ca0
Gerrit-Change-Number: 22772
Gerrit-PatchSet: 1
Gerrit-Owner: Richard Spiegel <richard.spiegel at silverbackltd.com>
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