<p>Richard Spiegel has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/22772">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/amd/common: Move Agesa related files<br><br>Move Agesa related files in soc/amd/common under block directory. Folder<br>soc/amd/common/block subfolders should mimic soc/intel/common/block<br>subfolders (one subfolder per subject). Header files should go to<br>soc/amd/common/block/include/amdblocks.<br><br>BUG=b:69262110<br>TEST=Build with no error gardenia and kahlee (no code change, just folder<br>reorg).<br><br>Change-Id: I5d3064625ddf8caaf370aabaf93165c6817f1ca0<br>Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com><br>---<br>M src/mainboard/amd/gardenia/BiosCallOuts.c<br>M src/mainboard/amd/gardenia/OemCustomize.c<br>M src/mainboard/amd/gardenia/bootblock/BiosCallOuts.c<br>M src/mainboard/amd/gardenia/bootblock/OemCustomize.c<br>M src/mainboard/amd/gardenia/mainboard.c<br>M src/mainboard/google/kahlee/BiosCallOuts.c<br>M src/mainboard/google/kahlee/OemCustomize.c<br>M src/mainboard/google/kahlee/bootblock/OemCustomize.c<br>M src/mainboard/google/kahlee/mainboard.c<br>M src/mainboard/google/kahlee/variants/baseboard/gpio.c<br>M src/mainboard/google/kahlee/variants/baseboard/include/baseboard/variants.h<br>M src/mainboard/google/kahlee/variants/kahlee/gpio.c<br>M src/soc/amd/common/Makefile.inc<br>R src/soc/amd/common/block/include/amdblocks/BiosCallOuts.h<br>R src/soc/amd/common/block/include/amdblocks/agesawrapper.h<br>R src/soc/amd/common/block/include/amdblocks/agesawrapper_call.h<br>M src/soc/amd/common/block/include/amdblocks/dimm_spd.h<br>M src/soc/amd/common/block/include/amdblocks/psp.h<br>A src/soc/amd/common/block/pi/Kconfig<br>A src/soc/amd/common/block/pi/Makefile.inc<br>R src/soc/amd/common/block/pi/agesawrapper.c<br>R src/soc/amd/common/block/pi/amd_late_init.c<br>R src/soc/amd/common/block/pi/def_callouts.c<br>R src/soc/amd/common/block/pi/heapmanager.c<br>M src/soc/amd/stoneyridge/BiosCallOuts.c<br>M src/soc/amd/stoneyridge/Kconfig<br>M src/soc/amd/stoneyridge/bootblock/bootblock.c<br>M src/soc/amd/stoneyridge/chip.c<br>M src/soc/amd/stoneyridge/early_setup.c<br>M src/soc/amd/stoneyridge/imc.c<br>M src/soc/amd/stoneyridge/include/fchec.h<br>M src/soc/amd/stoneyridge/northbridge.c<br>M src/soc/amd/stoneyridge/romstage.c<br>M src/soc/amd/stoneyridge/smbus_spd.c<br>M src/vendorcode/amd/pi/00670F00/Makefile.inc<br>35 files changed, 227 insertions(+), 166 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/22772/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/mainboard/amd/gardenia/BiosCallOuts.c b/src/mainboard/amd/gardenia/BiosCallOuts.c<br>index 398fadb..158642a 100644<br>--- a/src/mainboard/amd/gardenia/BiosCallOuts.c<br>+++ b/src/mainboard/amd/gardenia/BiosCallOuts.c<br>@@ -13,8 +13,8 @@<br> * GNU General Public License for more details.<br> */<br> <br>-#include <agesawrapper.h><br>-#include <BiosCallOuts.h><br>+#include <amdblocks/agesawrapper.h><br>+#include <amdblocks/BiosCallOuts.h><br> #include <soc/imc.h><br> #include <soc/southbridge.h><br> #include <stdlib.h><br>diff --git a/src/mainboard/amd/gardenia/OemCustomize.c b/src/mainboard/amd/gardenia/OemCustomize.c<br>index 8c7a8ac..f4d7769 100644<br>--- a/src/mainboard/amd/gardenia/OemCustomize.c<br>+++ b/src/mainboard/amd/gardenia/OemCustomize.c<br>@@ -14,7 +14,7 @@<br> */<br> <br> #include <chip.h><br>-#include <agesawrapper.h><br>+#include <amdblocks/agesawrapper.h><br> <br> #define DIMMS_PER_CHANNEL 2<br> #if DIMMS_PER_CHANNEL > MAX_DIMMS_PER_CH<br>diff --git a/src/mainboard/amd/gardenia/bootblock/BiosCallOuts.c b/src/mainboard/amd/gardenia/bootblock/BiosCallOuts.c<br>index 6b52162..7e60dae 100644<br>--- a/src/mainboard/amd/gardenia/bootblock/BiosCallOuts.c<br>+++ b/src/mainboard/amd/gardenia/bootblock/BiosCallOuts.c<br>@@ -13,8 +13,8 @@<br> * GNU General Public License for more details.<br> */<br> <br>-#include <agesawrapper.h><br>-#include <BiosCallOuts.h><br>+#include <amdblocks/agesawrapper.h><br>+#include <amdblocks/BiosCallOuts.h><br> #include <soc/southbridge.h><br> #include <stdlib.h><br> <br>diff --git a/src/mainboard/amd/gardenia/bootblock/OemCustomize.c b/src/mainboard/amd/gardenia/bootblock/OemCustomize.c<br>index 82b77f2..0d837cc 100644<br>--- a/src/mainboard/amd/gardenia/bootblock/OemCustomize.c<br>+++ b/src/mainboard/amd/gardenia/bootblock/OemCustomize.c<br>@@ -13,7 +13,7 @@<br> * GNU General Public License for more details.<br> */<br> <br>-#include <agesawrapper.h><br>+#include <amdblocks/agesawrapper.h><br> <br> #define FILECODE PROC_GNB_PCIE_FAMILY_0X15_F15PCIECOMPLEXCONFIG_FILECODE<br> <br>diff --git a/src/mainboard/amd/gardenia/mainboard.c b/src/mainboard/amd/gardenia/mainboard.c<br>index 25cf5b3..8df97fa 100644<br>--- a/src/mainboard/amd/gardenia/mainboard.c<br>+++ b/src/mainboard/amd/gardenia/mainboard.c<br>@@ -16,8 +16,8 @@<br> #include <console/console.h><br> #include <device/device.h><br> #include <arch/acpi.h><br>-#include <agesawrapper.h><br> #include <amdblocks/amd_pci_util.h><br>+#include <amdblocks/agesawrapper.h><br> <br> /***********************************************************<br> * These arrays set up the FCH PCI_INTR registers 0xC00/0xC01.<br>diff --git a/src/mainboard/google/kahlee/BiosCallOuts.c b/src/mainboard/google/kahlee/BiosCallOuts.c<br>index fd8465a..1c0df4d 100644<br>--- a/src/mainboard/google/kahlee/BiosCallOuts.c<br>+++ b/src/mainboard/google/kahlee/BiosCallOuts.c<br>@@ -13,8 +13,8 @@<br> * GNU General Public License for more details.<br> */<br> <br>-#include <agesawrapper.h><br>-#include <BiosCallOuts.h><br>+#include <amdblocks/agesawrapper.h><br>+#include <amdblocks/BiosCallOuts.h><br> #include <soc/southbridge.h><br> #include <stdlib.h><br> #include <baseboard/variants.h><br>diff --git a/src/mainboard/google/kahlee/OemCustomize.c b/src/mainboard/google/kahlee/OemCustomize.c<br>index c507526..8ab8e54 100644<br>--- a/src/mainboard/google/kahlee/OemCustomize.c<br>+++ b/src/mainboard/google/kahlee/OemCustomize.c<br>@@ -14,7 +14,7 @@<br> */<br> <br> #include <chip.h><br>-#include <agesawrapper.h><br>+#include <amdblocks/agesawrapper.h><br> <br> #define DIMMS_PER_CHANNEL 1<br> #if DIMMS_PER_CHANNEL > MAX_DIMMS_PER_CH<br>diff --git a/src/mainboard/google/kahlee/bootblock/OemCustomize.c b/src/mainboard/google/kahlee/bootblock/OemCustomize.c<br>index 0551184..997f010 100644<br>--- a/src/mainboard/google/kahlee/bootblock/OemCustomize.c<br>+++ b/src/mainboard/google/kahlee/bootblock/OemCustomize.c<br>@@ -13,7 +13,7 @@<br> * GNU General Public License for more details.<br> */<br> <br>-#include <agesawrapper.h><br>+#include <amdblocks/agesawrapper.h><br> <br> static const PCIe_PORT_DESCRIPTOR PortList[] = {<br> /* Initialize Port descriptor (PCIe port, Lanes 7:4, D2F1) for NC*/<br>diff --git a/src/mainboard/google/kahlee/mainboard.c b/src/mainboard/google/kahlee/mainboard.c<br>index fc13567..229cc5a 100644<br>--- a/src/mainboard/google/kahlee/mainboard.c<br>+++ b/src/mainboard/google/kahlee/mainboard.c<br>@@ -16,8 +16,8 @@<br> #include <console/console.h><br> #include <device/device.h><br> #include <arch/acpi.h><br>-#include <agesawrapper.h><br> #include <amdblocks/amd_pci_util.h><br>+#include <amdblocks/agesawrapper.h><br> #include <cbmem.h><br> #include <baseboard/variants.h><br> #include <boardid.h><br>diff --git a/src/mainboard/google/kahlee/variants/baseboard/gpio.c b/src/mainboard/google/kahlee/variants/baseboard/gpio.c<br>index 925ece9..86c87bb 100644<br>--- a/src/mainboard/google/kahlee/variants/baseboard/gpio.c<br>+++ b/src/mainboard/google/kahlee/variants/baseboard/gpio.c<br>@@ -13,7 +13,7 @@<br> * GNU General Public License for more details.<br> */<br> <br>-#include <agesawrapper.h><br>+#include <amdblocks/agesawrapper.h><br> #include <baseboard/variants.h><br> #include <soc/gpio.h><br> #include <soc/smi.h><br>diff --git a/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/variants.h<br>index 33054f5..9c54794 100644<br>--- a/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/variants.h<br>+++ b/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/variants.h<br>@@ -19,7 +19,7 @@<br> <br> #include <stddef.h><br> #include <soc/smi.h><br>-#include <agesawrapper.h><br>+#include <amdblocks/agesawrapper.h><br> <br> const GPIO_CONTROL *get_gpio_table(void);<br> const struct sci_source *get_gpe_table(size_t *num);<br>diff --git a/src/mainboard/google/kahlee/variants/kahlee/gpio.c b/src/mainboard/google/kahlee/variants/kahlee/gpio.c<br>index 97b0655..14424b7 100644<br>--- a/src/mainboard/google/kahlee/variants/kahlee/gpio.c<br>+++ b/src/mainboard/google/kahlee/variants/kahlee/gpio.c<br>@@ -13,7 +13,7 @@<br> * GNU General Public License for more details.<br> */<br> <br>-#include <agesawrapper.h><br>+#include <amdblocks/agesawrapper.h><br> #include <baseboard/variants.h><br> #include <soc/smi.h><br> #include <soc/southbridge.h><br>diff --git a/src/soc/amd/common/Makefile.inc b/src/soc/amd/common/Makefile.inc<br>index b485bb3..103c3bf 100644<br>--- a/src/soc/amd/common/Makefile.inc<br>+++ b/src/soc/amd/common/Makefile.inc<br>@@ -2,19 +2,6 @@<br> <br> CPPFLAGS_common += -I$(src)/soc/amd/common<br> <br>-bootblock-y += agesawrapper.c<br>-bootblock-y += def_callouts.c<br>-bootblock-y += heapmanager.c<br>-<br>-romstage-y += agesawrapper.c<br>-romstage-y += def_callouts.c<br>-romstage-y += heapmanager.c<br>-<br>-ramstage-y += agesawrapper.c<br>-ramstage-y += amd_late_init.c<br>-ramstage-y += def_callouts.c<br>-ramstage-y += heapmanager.c<br>-<br> subdirs-$(CONFIG_SOC_AMD_COMMON_BLOCK) += block<br> <br> endif<br>diff --git a/src/soc/amd/common/BiosCallOuts.h b/src/soc/amd/common/block/include/amdblocks/BiosCallOuts.h<br>similarity index 98%<br>rename from src/soc/amd/common/BiosCallOuts.h<br>rename to src/soc/amd/common/block/include/amdblocks/BiosCallOuts.h<br>index 5237d52..2302889 100644<br>--- a/src/soc/amd/common/BiosCallOuts.h<br>+++ b/src/soc/amd/common/block/include/amdblocks/BiosCallOuts.h<br>@@ -17,7 +17,7 @@<br> #ifndef __CALLOUTS_AMD_AGESA_H__<br> #define __CALLOUTS_AMD_AGESA_H__<br> <br>-#include "agesawrapper.h"<br>+#include <amdblocks/agesawrapper.h><br> <br> #define BIOS_HEAP_START_ADDRESS 0x010000000<br> #define BIOS_HEAP_SIZE 0x30000<br>diff --git a/src/soc/amd/common/agesawrapper.h b/src/soc/amd/common/block/include/amdblocks/agesawrapper.h<br>similarity index 100%<br>rename from src/soc/amd/common/agesawrapper.h<br>rename to src/soc/amd/common/block/include/amdblocks/agesawrapper.h<br>diff --git a/src/soc/amd/common/agesawrapper_call.h b/src/soc/amd/common/block/include/amdblocks/agesawrapper_call.h<br>similarity index 92%<br>rename from src/soc/amd/common/agesawrapper_call.h<br>rename to src/soc/amd/common/block/include/amdblocks/agesawrapper_call.h<br>index 01e2620..ea0206b 100644<br>--- a/src/soc/amd/common/agesawrapper_call.h<br>+++ b/src/soc/amd/common/block/include/amdblocks/agesawrapper_call.h<br>@@ -14,7 +14,7 @@<br> #ifndef __AGESAWRAPPER_CALL_H__<br> #define __AGESAWRAPPER_CALL_H__<br> <br>-#include "agesawrapper.h"<br>+#include <amdblocks/agesawrapper.h><br> #include <stdint.h><br> #include <console/console.h><br> <br>@@ -32,7 +32,8 @@<br> */<br> static const char *decodeAGESA_STATUS(AGESA_STATUS sret)<br> {<br>- const char *statusStrings[] = { "AGESA_SUCCESS", "AGESA_UNSUPPORTED",<br>+ static const char * const statusStrings[] = {<br>+ "AGESA_SUCCESS", "AGESA_UNSUPPORTED",<br> "AGESA_BOUNDS_CHK", "AGESA_ALERT",<br> "AGESA_WARNING", "AGESA_ERROR",<br> "AGESA_CRITICAL", "AGESA_FATAL"<br>diff --git a/src/soc/amd/common/block/include/amdblocks/dimm_spd.h b/src/soc/amd/common/block/include/amdblocks/dimm_spd.h<br>index e29edc5..60107c9 100644<br>--- a/src/soc/amd/common/block/include/amdblocks/dimm_spd.h<br>+++ b/src/soc/amd/common/block/include/amdblocks/dimm_spd.h<br>@@ -16,7 +16,7 @@<br> #ifndef __DIMMSPD_H__<br> #define __DIMMSPD_H__<br> <br>-#include <agesawrapper.h><br>+#include <amdblocks/agesawrapper.h><br> #include <stddef.h><br> #include <stdint.h><br> <br>diff --git a/src/soc/amd/common/block/include/amdblocks/psp.h b/src/soc/amd/common/block/include/amdblocks/psp.h<br>index 57ba649..4c9878a 100644<br>--- a/src/soc/amd/common/block/include/amdblocks/psp.h<br>+++ b/src/soc/amd/common/block/include/amdblocks/psp.h<br>@@ -16,7 +16,7 @@<br> #ifndef __AMD_PSP_H__<br> #define __AMD_PSP_H__<br> <br>-#include <agesawrapper.h><br>+#include <amdblocks/agesawrapper.h><br> #include <soc/pci_devs.h><br> #include <stdint.h><br> #include <compiler.h><br>diff --git a/src/soc/amd/common/block/pi/Kconfig b/src/soc/amd/common/block/pi/Kconfig<br>new file mode 100644<br>index 0000000..f11d6ed<br>--- /dev/null<br>+++ b/src/soc/amd/common/block/pi/Kconfig<br>@@ -0,0 +1,6 @@<br>+config SOC_AMD_COMMON_BLOCK_PI<br>+ bool<br>+ default n<br>+ help<br>+ This option builds functions that interface AMD's AGESA.<br>+<br>diff --git a/src/soc/amd/common/block/pi/Makefile.inc b/src/soc/amd/common/block/pi/Makefile.inc<br>new file mode 100644<br>index 0000000..de6bf78<br>--- /dev/null<br>+++ b/src/soc/amd/common/block/pi/Makefile.inc<br>@@ -0,0 +1,16 @@<br>+ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_PI),y)<br>+<br>+bootblock-y += agesawrapper.c<br>+bootblock-y += def_callouts.c<br>+bootblock-y += heapmanager.c<br>+<br>+romstage-y += agesawrapper.c<br>+romstage-y += def_callouts.c<br>+romstage-y += heapmanager.c<br>+<br>+ramstage-y += agesawrapper.c<br>+ramstage-y += amd_late_init.c<br>+ramstage-y += def_callouts.c<br>+ramstage-y += heapmanager.c<br>+<br>+endif<br>diff --git a/src/soc/amd/common/agesawrapper.c b/src/soc/amd/common/block/pi/agesawrapper.c<br>similarity index 74%<br>rename from src/soc/amd/common/agesawrapper.c<br>rename to src/soc/amd/common/block/pi/agesawrapper.c<br>index b939183..1c90eb3 100644<br>--- a/src/soc/amd/common/agesawrapper.c<br>+++ b/src/soc/amd/common/block/pi/agesawrapper.c<br>@@ -13,12 +13,12 @@<br> * GNU General Public License for more details.<br> */<br> <br>-#include "agesawrapper.h"<br>+#include <amdblocks/agesawrapper.h><br> #include <cbfs.h><br> #include <cbmem.h><br> #include <delay.h><br> #include <cpu/x86/mtrr.h><br>-#include <BiosCallOuts.h><br>+#include <amdblocks/BiosCallOuts.h><br> #include <string.h><br> <br> void __attribute__((weak)) SetMemParams(AMD_POST_PARAMS *PostParams) {}<br>@@ -57,13 +57,20 @@<br> AmdParamStruct.StdHeader.ImageBasePtr = 0;<br> AmdCreateStruct (&AmdParamStruct);<br> <br>- AmdResetParams.FchInterface.Xhci0Enable = IS_ENABLED(CONFIG_STONEYRIDGE_XHCI_ENABLE);<br>+ AmdResetParams.FchInterface.Xhci0Enable =<br>+ IS_ENABLED(CONFIG_STONEYRIDGE_XHCI_ENABLE);<br> <br>- AmdResetParams.FchInterface.SataEnable = !((CONFIG_STONEYRIDGE_SATA_MODE == 0) || (CONFIG_STONEYRIDGE_SATA_MODE == 3));<br>- AmdResetParams.FchInterface.IdeEnable = (CONFIG_STONEYRIDGE_SATA_MODE == 0) || (CONFIG_STONEYRIDGE_SATA_MODE == 3);<br>+ AmdResetParams.FchInterface.SataEnable =<br>+ !((CONFIG_STONEYRIDGE_SATA_MODE == 0) ||<br>+ (CONFIG_STONEYRIDGE_SATA_MODE == 3));<br>+ AmdResetParams.FchInterface.IdeEnable =<br>+ (CONFIG_STONEYRIDGE_SATA_MODE == 0) ||<br>+ (CONFIG_STONEYRIDGE_SATA_MODE == 3);<br> <br> status = AmdInitReset(&AmdResetParams);<br>- if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(AmdParamStruct.StdHeader.HeapStatus);<br>+ if (status != AGESA_SUCCESS)<br>+ agesawrapper_amdreadeventlog(<br>+ AmdParamStruct.StdHeader.HeapStatus);<br> AmdReleaseStruct (&AmdParamStruct);<br> return status;<br> }<br>@@ -90,7 +97,9 @@<br> AmdEarlyParamsPtr->GnbConfig.PsppPolicy = PsppDisabled;<br> status = AmdInitEarly ((AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr);<br> <br>- if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(AmdParamStruct.StdHeader.HeapStatus);<br>+ if (status != AGESA_SUCCESS)<br>+ agesawrapper_amdreadeventlog(<br>+ AmdParamStruct.StdHeader.HeapStatus);<br> AmdReleaseStruct (&AmdParamStruct);<br> <br> return status;<br>@@ -132,34 +141,42 @@<br> /* If UMA is enabled we currently have it below TOP_MEM as well.<br> * UMA may or may not be cacheable, so Sub4GCacheTop could be<br> * higher than UmaBase. With UMA_NONE we see UmaBase==0. */<br>- if (PostParams->MemConfig.UmaBase)<br>- backup_top_of_low_cacheable(PostParams->MemConfig.UmaBase << 16);<br>- else<br>- backup_top_of_low_cacheable(PostParams->MemConfig.Sub4GCacheTop);<br>-<br>+ if (PostParams->MemConfig.UmaBase) {<br>+ backup_top_of_low_cacheable(PostParams->MemConfig.<br>+ UmaBase << 16);<br>+ } else {<br>+ backup_top_of_low_cacheable(PostParams->MemConfig.<br>+ Sub4GCacheTop);<br>+ }<br> <br> printk(<br> BIOS_SPEW,<br> "setup_uma_memory: umamode %s\n",<br>- (PostParams->MemConfig.UmaMode == UMA_AUTO) ? "UMA_AUTO" :<br>- (PostParams->MemConfig.UmaMode == UMA_SPECIFIED) ? "UMA_SPECIFIED" :<br>- (PostParams->MemConfig.UmaMode == UMA_NONE) ? "UMA_NONE" :<br>- "unknown"<br>+ (PostParams->MemConfig.UmaMode == UMA_AUTO) ?<br>+ "UMA_AUTO" :<br>+ (PostParams->MemConfig.UmaMode == UMA_SPECIFIED) ?<br>+ "UMA_SPECIFIED" :<br>+ (PostParams->MemConfig.UmaMode == UMA_NONE) ?<br>+ "UMA_NONE" : "unknown"<br> );<br> printk(<br> BIOS_SPEW,<br>- "setup_uma_memory: syslimit 0x%08llX, bottomio 0x%08lx\n",<br>- (unsigned long long)(PostParams->MemConfig.SysLimit) << 16,<br>+ "setup_uma_memory: syslimit 0x%08llX,"<br>+ " bottomio 0x%08lx\n",<br>+ (unsigned long long)(PostParams-><br>+ MemConfig.SysLimit) << 16,<br> (unsigned long)(PostParams->MemConfig.BottomIo) << 16<br> );<br> printk(<br> BIOS_SPEW,<br> "setup_uma_memory: uma size %luMB, uma start 0x%08lx\n",<br>- (unsigned long)(PostParams->MemConfig.UmaSize) >> (20 - 16),<br>+ (unsigned long)(PostParams->MemConfig.UmaSize) >><br>+ (20 - 16),<br> (unsigned long)(PostParams->MemConfig.UmaBase) << 16<br> );<br> <br>- if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(PostParams->StdHeader.HeapStatus);<br>+ if (status != AGESA_SUCCESS)<br>+ agesawrapper_amdreadeventlog(PostParams->StdHeader.HeapStatus);<br> AmdReleaseStruct (&AmdParamStruct);<br> <br> return status;<br>@@ -184,13 +201,19 @@<br> <br> EnvParam->FchInterface.AzaliaController = AzEnable;<br> EnvParam->FchInterface.SataClass = CONFIG_STONEYRIDGE_SATA_MODE;<br>- EnvParam->FchInterface.SataEnable = !((CONFIG_STONEYRIDGE_SATA_MODE == 0) || (CONFIG_STONEYRIDGE_SATA_MODE == 3));<br>- EnvParam->FchInterface.IdeEnable = (CONFIG_STONEYRIDGE_SATA_MODE == 0) || (CONFIG_STONEYRIDGE_SATA_MODE == 3);<br>- EnvParam->FchInterface.SataIdeMode = (CONFIG_STONEYRIDGE_SATA_MODE == 3);<br>+ EnvParam->FchInterface.SataEnable =<br>+ !((CONFIG_STONEYRIDGE_SATA_MODE == 0) ||<br>+ (CONFIG_STONEYRIDGE_SATA_MODE == 3));<br>+ EnvParam->FchInterface.IdeEnable =<br>+ (CONFIG_STONEYRIDGE_SATA_MODE == 0) ||<br>+ (CONFIG_STONEYRIDGE_SATA_MODE == 3);<br>+ EnvParam->FchInterface.SataIdeMode =<br>+ (CONFIG_STONEYRIDGE_SATA_MODE == 3);<br> EnvParam->GnbEnvConfiguration.IommuSupport = FALSE;<br> <br> status = AmdInitEnv (EnvParam);<br>- if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(EnvParam->StdHeader.HeapStatus);<br>+ if (status != AGESA_SUCCESS)<br>+ agesawrapper_amdreadeventlog(EnvParam->StdHeader.HeapStatus);<br> /* Initialize Subordinate Bus Number and Secondary Bus Number<br> * In platform BIOS this address is allocated by PCI enumeration code<br> Modify D1F0x18<br>@@ -200,7 +223,7 @@<br> }<br> <br> #ifndef __PRE_RAM__<br>-VOID* agesawrapper_getlateinitptr (int pick)<br>+VOID *agesawrapper_getlateinitptr (int pick)<br> {<br> switch (pick) {<br> case PICK_DMI:<br>@@ -248,17 +271,26 @@<br> AmdCreateStruct (&AmdParamStruct);<br> MidParam = (AMD_MID_PARAMS *)AmdParamStruct.NewStructPtr;<br> <br>- MidParam->GnbMidConfiguration.iGpuVgaMode = 0;/* 0 iGpuVgaAdapter, 1 iGpuVgaNonAdapter; */<br>+ /* 0 iGpuVgaAdapter, 1 iGpuVgaNonAdapter; */<br>+ MidParam->GnbMidConfiguration.iGpuVgaMode = 0;<br>+<br> MidParam->GnbMidConfiguration.GnbIoapicAddress = 0xFEC20000;<br> <br> MidParam->FchInterface.AzaliaController = AzEnable;<br> MidParam->FchInterface.SataClass = CONFIG_STONEYRIDGE_SATA_MODE;<br>- MidParam->FchInterface.SataEnable = !((CONFIG_STONEYRIDGE_SATA_MODE == 0) || (CONFIG_STONEYRIDGE_SATA_MODE == 3));<br>- MidParam->FchInterface.IdeEnable = (CONFIG_STONEYRIDGE_SATA_MODE == 0) || (CONFIG_STONEYRIDGE_SATA_MODE == 3);<br>- MidParam->FchInterface.SataIdeMode = (CONFIG_STONEYRIDGE_SATA_MODE == 3);<br>+ MidParam->FchInterface.SataEnable =<br>+ !((CONFIG_STONEYRIDGE_SATA_MODE == 0) ||<br>+ (CONFIG_STONEYRIDGE_SATA_MODE == 3));<br>+ MidParam->FchInterface.IdeEnable =<br>+ (CONFIG_STONEYRIDGE_SATA_MODE == 0) ||<br>+ (CONFIG_STONEYRIDGE_SATA_MODE == 3);<br>+ MidParam->FchInterface.SataIdeMode =<br>+ (CONFIG_STONEYRIDGE_SATA_MODE == 3);<br> <br> status = AmdInitMid ((AMD_MID_PARAMS *)AmdParamStruct.NewStructPtr);<br>- if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(AmdParamStruct.StdHeader.HeapStatus);<br>+ if (status != AGESA_SUCCESS)<br>+ agesawrapper_amdreadeventlog(<br>+ AmdParamStruct.StdHeader.HeapStatus);<br> AmdReleaseStruct (&AmdParamStruct);<br> <br> return status;<br>@@ -281,12 +313,16 @@<br> AmdParamStruct.StdHeader.Func = 0;<br> AmdParamStruct.StdHeader.ImageBasePtr = 0;<br> <br>- /* NOTE: if not call amdcreatestruct, the initializer(AmdInitLateInitializer) would not be called */<br>+ /*<br>+ * NOTE: if not call amdcreatestruct, the initializer<br>+ * (AmdInitLateInitializer) would not be called<br>+ */<br> AmdCreateStruct(&AmdParamStruct);<br> AmdLateParams = (AMD_LATE_PARAMS *)AmdParamStruct.NewStructPtr;<br> Status = AmdInitLate(AmdLateParams);<br> if (Status != AGESA_SUCCESS) {<br>- agesawrapper_amdreadeventlog(AmdLateParams->StdHeader.HeapStatus);<br>+ agesawrapper_amdreadeventlog(<br>+ AmdLateParams->StdHeader.HeapStatus);<br> ASSERT(Status == AGESA_SUCCESS);<br> }<br> <br>@@ -302,8 +338,9 @@<br> printk(BIOS_DEBUG, "DmiTable:%x, AcpiPstatein: %x, AcpiSrat:%x,"<br> "AcpiSlit:%x, Mce:%x, Cmc:%x,"<br> "Alib:%x, AcpiIvrs:%x in %s\n",<br>- (unsigned int)DmiTable, (unsigned int)AcpiPstate, (unsigned int)AcpiSrat,<br>- (unsigned int)AcpiSlit, (unsigned int)AcpiWheaMce, (unsigned int)AcpiWheaCmc,<br>+ (unsigned int)DmiTable, (unsigned int)AcpiPstate,<br>+ (unsigned int)AcpiSrat, (unsigned int)AcpiSlit,<br>+ (unsigned int)AcpiWheaMce, (unsigned int)AcpiWheaCmc,<br> (unsigned int)AcpiAlib, (unsigned int)AcpiIvrs, __func__);<br> <br> /* AmdReleaseStruct (&AmdParamStruct); */<br>@@ -352,9 +389,16 @@<br> AmdEventParams.StdHeader.HeapStatus = HeapStatus;<br> Status = AmdReadEventLog (&AmdEventParams);<br> while (AmdEventParams.EventClass != 0) {<br>- printk(BIOS_DEBUG,"\nEventLog: EventClass = %x, EventInfo = %x.\n", (unsigned int)AmdEventParams.EventClass,(unsigned int)AmdEventParams.EventInfo);<br>- printk(BIOS_DEBUG," Param1 = %x, Param2 = %x.\n",(unsigned int)AmdEventParams.DataParam1, (unsigned int)AmdEventParams.DataParam2);<br>- printk(BIOS_DEBUG," Param3 = %x, Param4 = %x.\n",(unsigned int)AmdEventParams.DataParam3, (unsigned int)AmdEventParams.DataParam4);<br>+ printk(BIOS_DEBUG,<br>+ "\nEventLog: EventClass = %x, EventInfo = %x.\n",<br>+ (unsigned int)AmdEventParams.EventClass,<br>+ (unsigned int)AmdEventParams.EventInfo);<br>+ printk(BIOS_DEBUG," Param1 = %x, Param2 = %x.\n",<br>+ (unsigned int)AmdEventParams.DataParam1,<br>+ (unsigned int)AmdEventParams.DataParam2);<br>+ printk(BIOS_DEBUG," Param3 = %x, Param4 = %x.\n",<br>+ (unsigned int)AmdEventParams.DataParam3,<br>+ (unsigned int)AmdEventParams.DataParam4);<br> Status = AmdReadEventLog (&AmdEventParams);<br> }<br> <br>@@ -363,9 +407,9 @@<br> <br> const void *agesawrapper_locate_module (const CHAR8 name[8])<br> {<br>- const void* agesa;<br>- const AMD_IMAGE_HEADER* image;<br>- const AMD_MODULE_HEADER* module;<br>+ const void *agesa;<br>+ const AMD_IMAGE_HEADER *image;<br>+ const AMD_MODULE_HEADER *module;<br> size_t file_size;<br> <br> agesa = cbfs_boot_map_with_leak((const char *)CONFIG_AGESA_CBFS_NAME,<br>@@ -374,7 +418,7 @@<br> if (!agesa)<br> return NULL;<br> image = LibAmdLocateImage(agesa, agesa + file_size - 1, 4096, name);<br>- module = (AMD_MODULE_HEADER*)image->ModuleInfoOffset;<br>+ module = (AMD_MODULE_HEADER *)image->ModuleInfoOffset;<br> <br> return module;<br> }<br>diff --git a/src/soc/amd/common/amd_late_init.c b/src/soc/amd/common/block/pi/amd_late_init.c<br>similarity index 92%<br>rename from src/soc/amd/common/amd_late_init.c<br>rename to src/soc/amd/common/block/pi/amd_late_init.c<br>index 3aee23c..65667b9 100644<br>--- a/src/soc/amd/common/amd_late_init.c<br>+++ b/src/soc/amd/common/block/pi/amd_late_init.c<br>@@ -20,8 +20,8 @@<br> #include <device/pci_def.h><br> #include <device/pci_ops.h><br> <br>-#include <agesawrapper.h><br>-#include <agesawrapper_call.h><br>+#include <amdblocks/agesawrapper.h><br>+#include <amdblocks/agesawrapper_call.h><br> <br> static void agesawrapper_post_device(void *unused)<br> {<br>diff --git a/src/soc/amd/common/def_callouts.c b/src/soc/amd/common/block/pi/def_callouts.c<br>similarity index 98%<br>rename from src/soc/amd/common/def_callouts.c<br>rename to src/soc/amd/common/block/pi/def_callouts.c<br>index cc7f556..c05d4de 100644<br>--- a/src/soc/amd/common/def_callouts.c<br>+++ b/src/soc/amd/common/block/pi/def_callouts.c<br>@@ -19,9 +19,9 @@<br> #include <cpu/x86/mp.h><br> #include <timer.h><br> #include <amdlib.h><br>-#include <BiosCallOuts.h><br>-#include "agesawrapper.h"<br>-#include <agesawrapper_call.h><br>+#include <amdblocks/BiosCallOuts.h><br>+#include <amdblocks/agesawrapper.h><br>+#include <amdblocks/agesawrapper_call.h><br> #include <reset.h><br> #include <soc/southbridge.h><br> <br>diff --git a/src/soc/amd/common/heapmanager.c b/src/soc/amd/common/block/pi/heapmanager.c<br>similarity index 78%<br>rename from src/soc/amd/common/heapmanager.c<br>rename to src/soc/amd/common/block/pi/heapmanager.c<br>index b991514..a7d7e90 100644<br>--- a/src/soc/amd/common/heapmanager.c<br>+++ b/src/soc/amd/common/block/pi/heapmanager.c<br>@@ -12,10 +12,10 @@<br> */<br> <br> <br>-#include "agesawrapper.h"<br>+#include <amdblocks/agesawrapper.h><br> #include <amdlib.h><br> #include <arch/acpi.h><br>-#include <BiosCallOuts.h><br>+#include <amdblocks/BiosCallOuts.h><br> #include <cbmem.h><br> #include <string.h><br> <br>@@ -113,17 +113,31 @@<br> while (FreedNodeOffset != 0) { /* todo: simplify this */<br> FreedNodePtr = (BIOS_BUFFER_NODE *)(BiosHeapBaseAddr<br> + FreedNodeOffset);<br>- if (FreedNodePtr->BufferSize >= (AllocParams->BufferLength + sizeof(BIOS_BUFFER_NODE))) {<br>+ if (FreedNodePtr->BufferSize >=<br>+ (AllocParams->BufferLength +<br>+ sizeof(BIOS_BUFFER_NODE))) {<br> if (BestFitNodeOffset == 0) {<br>- /* First node that fits the requested buffer size */<br>+ /*<br>+ * First node that fits the requested<br>+ * buffer size<br>+ */<br> BestFitNodeOffset = FreedNodeOffset;<br> BestFitPrevNodeOffset = PrevNodeOffset;<br> } else {<br>- /* Find out whether current node is a better fit than the previous nodes */<br>- BestFitNodePtr = (BIOS_BUFFER_NODE *)(BiosHeapBaseAddr + BestFitNodeOffset);<br>- if (BestFitNodePtr->BufferSize > FreedNodePtr->BufferSize) {<br>- BestFitNodeOffset = FreedNodeOffset;<br>- BestFitPrevNodeOffset = PrevNodeOffset;<br>+ /*<br>+ * Find out whether current node is a<br>+ * betterfit than the previous nodes<br>+ */<br>+ BestFitNodePtr =(BIOS_BUFFER_NODE *)<br>+ (BiosHeapBaseAddr +<br>+ BestFitNodeOffset);<br>+ if (BestFitNodePtr->BufferSize ><br>+ FreedNodePtr->BufferSize) {<br>+<br>+ BestFitNodeOffset =<br>+ FreedNodeOffset;<br>+ BestFitPrevNodeOffset =<br>+ PrevNodeOffset;<br> }<br> }<br> }<br>@@ -131,66 +145,60 @@<br> FreedNodeOffset = FreedNodePtr->NextNodeOffset;<br> } /* end of while loop */<br> <br>- if (BestFitNodeOffset == 0) {<br>- /* If we could not find a node that fits the requested<br>+ if (BestFitNodeOffset == 0)<br>+ /*<br>+ * If we could not find a node that fits the requested<br> * buffer size, return AGESA_BOUNDS_CHK.<br> */<br> return AGESA_BOUNDS_CHK;<br>+<br>+ BestFitNodePtr = (BIOS_BUFFER_NODE *)(BiosHeapBaseAddr<br>+ + BestFitNodeOffset);<br>+ BestFitPrevNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr +<br>+ BestFitPrevNodeOffset);<br>+<br>+ /*<br>+ * If BestFitNode is larger than the requested buffer,<br>+ * fragment the node further<br>+ */<br>+ if (BestFitNodePtr->BufferSize > (AllocParams->BufferLength +<br>+ sizeof(BIOS_BUFFER_NODE))) {<br>+ NextFreeOffset = BestFitNodeOffset +<br>+ AllocParams->BufferLength +<br>+ sizeof(BIOS_BUFFER_NODE);<br>+ NextFreePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr +<br>+ NextFreeOffset);<br>+ NextFreePtr->BufferSize = BestFitNodePtr->BufferSize -<br>+ (AllocParams->BufferLength +<br>+ sizeof(BIOS_BUFFER_NODE));<br>+ NextFreePtr->NextNodeOffset =<br>+ BestFitNodePtr->NextNodeOffset;<br> } else {<br>- BestFitNodePtr = (BIOS_BUFFER_NODE *)(BiosHeapBaseAddr<br>- + BestFitNodeOffset);<br>- BestFitPrevNodePtr = (BIOS_BUFFER_NODE *)<br>- (BiosHeapBaseAddr<br>- + BestFitPrevNodeOffset);<br>-<br>- /* If BestFitNode is larger than the requested buffer,<br>- * fragment the node further<br>+ /*<br>+ * Otherwise, next free node is<br>+ * NextNodeOffset of BestFitNode<br> */<br>- if (BestFitNodePtr->BufferSize ><br>- (AllocParams->BufferLength<br>- + sizeof(BIOS_BUFFER_NODE))) {<br>- NextFreeOffset = BestFitNodeOffset<br>- + AllocParams->BufferLength<br>- + sizeof(BIOS_BUFFER_NODE);<br>-<br>- NextFreePtr = (BIOS_BUFFER_NODE *)<br>- (BiosHeapBaseAddr<br>- + NextFreeOffset);<br>- NextFreePtr->BufferSize =<br>- BestFitNodePtr->BufferSize<br>- - (AllocParams->BufferLength<br>- + sizeof(BIOS_BUFFER_NODE));<br>- NextFreePtr->NextNodeOffset =<br>- BestFitNodePtr->NextNodeOffset;<br>- } else {<br>- /* Otherwise, next free node is<br>- * NextNodeOffset of BestFitNode<br>- */<br>- NextFreeOffset = BestFitNodePtr->NextNodeOffset;<br>- }<br>-<br>- /* If BestFitNode is the first buffer in the list, then<br>- * update StartOfFreedNodes to reflect new free node.<br>- */<br>- if (BestFitNodeOffset ==<br>- BiosHeapBasePtr->StartOfFreedNodes)<br>- BiosHeapBasePtr->StartOfFreedNodes =<br>- NextFreeOffset;<br>- else<br>- BestFitPrevNodePtr->NextNodeOffset =<br>- NextFreeOffset;<br>-<br>- /* Add BestFitNode to the list of Allocated nodes */<br>- CurrNodePtr->NextNodeOffset = BestFitNodeOffset;<br>- BestFitNodePtr->BufferSize = AllocParams->BufferLength;<br>- BestFitNodePtr->BufferHandle =<br>- AllocParams->BufferHandle;<br>- BestFitNodePtr->NextNodeOffset = 0;<br>-<br>- /* Remove BestFitNode from list of Freed nodes */<br>- AllocParams->BufferPointer = (UINT8 *)BestFitNodePtr<br>- + sizeof(BIOS_BUFFER_NODE);<br>+ NextFreeOffset = BestFitNodePtr->NextNodeOffset;<br> }<br>+<br>+ /*<br>+ * If BestFitNode is the first buffer in the list, then<br>+ * update StartOfFreedNodes to reflect new free node.<br>+ */<br>+ if (BestFitNodeOffset == BiosHeapBasePtr->StartOfFreedNodes)<br>+ BiosHeapBasePtr->StartOfFreedNodes = NextFreeOffset;<br>+ else<br>+ BestFitPrevNodePtr->NextNodeOffset = NextFreeOffset;<br>+<br>+ /* Add BestFitNode to the list of Allocated nodes */<br>+ CurrNodePtr->NextNodeOffset = BestFitNodeOffset;<br>+ BestFitNodePtr->BufferSize = AllocParams->BufferLength;<br>+ BestFitNodePtr->BufferHandle = AllocParams->BufferHandle;<br>+ BestFitNodePtr->NextNodeOffset = 0;<br>+<br>+ /* Remove BestFitNode from list of Freed nodes */<br>+ AllocParams->BufferPointer = (UINT8 *)BestFitNodePtr +<br>+ sizeof(BIOS_BUFFER_NODE);<br> }<br> <br> return AGESA_SUCCESS;<br>@@ -302,11 +310,10 @@<br> NextNodePtr->BufferSize = 0;<br> NextNodePtr->NextNodeOffset = 0;<br> } else {<br>- /*AllocNodePtr->NextNodeOffset =<br>- * FreedNodePtr->NextNodeOffset; */<br> AllocNodePtr->NextNodeOffset = NextNodeOffset;<br> }<br>- /* If deallocated node is adjacent to the previous node,<br>+ /*<br>+ * If deallocated node is adjacent to the previous node,<br> * concatenate both nodes.<br> */<br> PrevNodePtr = (BIOS_BUFFER_NODE *)(BiosHeapBaseAddr<br>@@ -347,11 +354,10 @@<br> AllocParams->BufferPointer = NULL;<br> AllocParams->BufferLength = 0;<br> return AGESA_BOUNDS_CHK;<br>- } else {<br>- AllocNodeOffset = AllocNodePtr->NextNodeOffset;<br>- AllocNodePtr = (BIOS_BUFFER_NODE *)(BiosHeapBaseAddr<br>- + AllocNodeOffset);<br> }<br>+ AllocNodeOffset = AllocNodePtr->NextNodeOffset;<br>+ AllocNodePtr = (BIOS_BUFFER_NODE *)(BiosHeapBaseAddr +<br>+ AllocNodeOffset);<br> }<br> <br> AllocParams->BufferPointer = (UINT8 *)((UINT8 *)AllocNodePtr<br>diff --git a/src/soc/amd/stoneyridge/BiosCallOuts.c b/src/soc/amd/stoneyridge/BiosCallOuts.c<br>index 87eccaa..f6ac187 100644<br>--- a/src/soc/amd/stoneyridge/BiosCallOuts.c<br>+++ b/src/soc/amd/stoneyridge/BiosCallOuts.c<br>@@ -17,12 +17,12 @@<br> <br> #include <device/device.h><br> #include <device/pci_def.h><br>-#include <BiosCallOuts.h><br>+#include <amdblocks/BiosCallOuts.h><br> #include <soc/southbridge.h><br> #include <soc/pci_devs.h><br> #include <stdlib.h><br> <br>-#include <agesawrapper.h><br>+#include <amdblocks/agesawrapper.h><br> #include <amdlib.h><br> #include <amdblocks/dimm_spd.h><br> #include "chip.h"<br>diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig<br>index fe4e4ef..4e2fde6 100644<br>--- a/src/soc/amd/stoneyridge/Kconfig<br>+++ b/src/soc/amd/stoneyridge/Kconfig<br>@@ -46,9 +46,10 @@<br> select SOC_AMD_PI<br> select SOC_AMD_COMMON<br> select SOC_AMD_COMMON_BLOCK<br>- select SOC_AMD_COMMON_BLOCK_PCI<br>- select SOC_AMD_COMMON_BLOCK_PSP<br> select SOC_AMD_COMMON_BLOCK_CAR<br>+ select SOC_AMD_COMMON_BLOCK_PCI<br>+ select SOC_AMD_COMMON_BLOCK_PI<br>+ select SOC_AMD_COMMON_BLOCK_PSP<br> select SOC_AMD_COMMON_BLOCK_SPI<br> select C_ENVIRONMENT_BOOTBLOCK<br> select BOOTBLOCK_CONSOLE<br>diff --git a/src/soc/amd/stoneyridge/bootblock/bootblock.c b/src/soc/amd/stoneyridge/bootblock/bootblock.c<br>index abe06fb..030c990 100644<br>--- a/src/soc/amd/stoneyridge/bootblock/bootblock.c<br>+++ b/src/soc/amd/stoneyridge/bootblock/bootblock.c<br>@@ -22,8 +22,8 @@<br> #include <cpu/amd/amdfam15.h><br> #include <smp/node.h><br> #include <bootblock_common.h><br>-#include <agesawrapper.h><br>-#include <agesawrapper_call.h><br>+#include <amdblocks/agesawrapper.h><br>+#include <amdblocks/agesawrapper_call.h><br> #include <soc/pci_devs.h><br> #include <soc/northbridge.h><br> #include <soc/southbridge.h><br>diff --git a/src/soc/amd/stoneyridge/chip.c b/src/soc/amd/stoneyridge/chip.c<br>index 8e4ab2e..8d6a8e4 100644<br>--- a/src/soc/amd/stoneyridge/chip.c<br>+++ b/src/soc/amd/stoneyridge/chip.c<br>@@ -24,8 +24,8 @@<br> #include <soc/northbridge.h><br> #include <soc/southbridge.h><br> #include <amdblocks/psp.h><br>-#include <agesawrapper.h><br>-#include <agesawrapper_call.h><br>+#include <amdblocks/agesawrapper.h><br>+#include <amdblocks/agesawrapper_call.h><br> <br> struct device_operations cpu_bus_ops = {<br> .read_resources = DEVICE_NOOP,<br>diff --git a/src/soc/amd/stoneyridge/early_setup.c b/src/soc/amd/stoneyridge/early_setup.c<br>index 09eb8b6..5bf32f8 100644<br>--- a/src/soc/amd/stoneyridge/early_setup.c<br>+++ b/src/soc/amd/stoneyridge/early_setup.c<br>@@ -13,7 +13,7 @@<br> * GNU General Public License for more details.<br> */<br> <br>-#include <agesawrapper.h><br>+#include <amdblocks/agesawrapper.h><br> #include <assert.h><br> #include <stdint.h><br> #include <arch/io.h><br>diff --git a/src/soc/amd/stoneyridge/imc.c b/src/soc/amd/stoneyridge/imc.c<br>index f7eed20..5d883d9 100644<br>--- a/src/soc/amd/stoneyridge/imc.c<br>+++ b/src/soc/amd/stoneyridge/imc.c<br>@@ -15,7 +15,7 @@<br> <br> #define __SIMPLE_DEVICE__<br> <br>-#include <agesawrapper.h><br>+#include <amdblocks/agesawrapper.h><br> #include <soc/imc.h><br> #include <arch/io.h><br> #include <device/device.h><br>diff --git a/src/soc/amd/stoneyridge/include/fchec.h b/src/soc/amd/stoneyridge/include/fchec.h<br>index e5e9cfd..80125ec 100644<br>--- a/src/soc/amd/stoneyridge/include/fchec.h<br>+++ b/src/soc/amd/stoneyridge/include/fchec.h<br>@@ -16,7 +16,7 @@<br> #ifndef __AMD_STONEY_FCHEC__<br> #define __AMD_STONEY_FCHEC__<br> <br>-#include <agesawrapper.h><br>+#include <amdblocks/agesawrapper.h><br> #include <soc/imc.h><br> <br> void agesawrapper_fchecfancontrolservice(void);<br>diff --git a/src/soc/amd/stoneyridge/northbridge.c b/src/soc/amd/stoneyridge/northbridge.c<br>index 3eb8e8d..27b5388 100644<br>--- a/src/soc/amd/stoneyridge/northbridge.c<br>+++ b/src/soc/amd/stoneyridge/northbridge.c<br>@@ -28,8 +28,8 @@<br> #include <device/device.h><br> #include <device/pci.h><br> #include <device/pci_ids.h><br>-#include <agesawrapper.h><br>-#include <agesawrapper_call.h><br>+#include <amdblocks/agesawrapper.h><br>+#include <amdblocks/agesawrapper_call.h><br> #include <soc/northbridge.h><br> #include <soc/southbridge.h><br> #include <soc/pci_devs.h><br>diff --git a/src/soc/amd/stoneyridge/romstage.c b/src/soc/amd/stoneyridge/romstage.c<br>index 32dee5a..7c738ad 100644<br>--- a/src/soc/amd/stoneyridge/romstage.c<br>+++ b/src/soc/amd/stoneyridge/romstage.c<br>@@ -24,8 +24,8 @@<br> #include <device/device.h><br> #include <chip.h><br> #include <program_loading.h><br>-#include <agesawrapper.h><br>-#include <agesawrapper_call.h><br>+#include <amdblocks/agesawrapper.h><br>+#include <amdblocks/agesawrapper_call.h><br> #include <soc/northbridge.h><br> #include <soc/southbridge.h><br> #include <amdblocks/psp.h><br>diff --git a/src/soc/amd/stoneyridge/smbus_spd.c b/src/soc/amd/stoneyridge/smbus_spd.c<br>index acd907e..6027400 100644<br>--- a/src/soc/amd/stoneyridge/smbus_spd.c<br>+++ b/src/soc/amd/stoneyridge/smbus_spd.c<br>@@ -13,7 +13,7 @@<br> * GNU General Public License for more details.<br> */<br> <br>-#include <agesawrapper.h><br>+#include <amdblocks/agesawrapper.h><br> #include <device/pci_def.h><br> #include <device/device.h><br> #include <soc/southbridge.h><br>diff --git a/src/vendorcode/amd/pi/00670F00/Makefile.inc b/src/vendorcode/amd/pi/00670F00/Makefile.inc<br>index d59b553..bf04e50 100644<br>--- a/src/vendorcode/amd/pi/00670F00/Makefile.inc<br>+++ b/src/vendorcode/amd/pi/00670F00/Makefile.inc<br>@@ -50,7 +50,7 @@<br> AGESA_INC += $(BINARY_PI_INC)<br> <br> AGESA_INC += -I$(src)/soc/amd/stoneyridge/include<br>-AGESA_INC += -I$(src)/soc/amd/common<br>+AGESA_INC += -I$(src)/soc/amd/common/block/include/amdblocks<br> <br> AGESA_INC += -I$(src)/arch/x86/include<br> AGESA_INC += -I$(src)/include<br></pre><p>To view, visit <a href="https://review.coreboot.org/22772">change 22772</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
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<div style="display:none"> Gerrit-Change-Id: I5d3064625ddf8caaf370aabaf93165c6817f1ca0 </div>
<div style="display:none"> Gerrit-Change-Number: 22772 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Richard Spiegel <richard.spiegel@silverbackltd.com> </div>