[coreboot-gerrit] Change in coreboot[master]: soc/amd/common: Move files to common/block
Richard Spiegel (Code Review)
gerrit at coreboot.org
Thu Dec 7 00:15:50 CET 2017
Richard Spiegel has uploaded this change for review. ( https://review.coreboot.org/22765
Change subject: soc/amd/common: Move files to common/block
......................................................................
soc/amd/common: Move files to common/block
The following files need to be moved: amd_pci_util.c, amd_pci_util.h and
spi.c. The remaining files are AGESA related and will be part of a separate
issue/commit. After AGESA related files are moved, Kconfig and Makefile.inc
will be removed too, thus rending a clean soc/amd/common folder.
BUG=b:62240201
TEST=Build with no error.
Change-Id: I3f965afa21124d4874d3b7bfe0f404a58b070e23
Signed-off-by: Richard Spiegel <richard.spiegel at silverbackltd.com>
---
M src/mainboard/amd/gardenia/mainboard.c
M src/mainboard/amd/gardenia/mptable.c
M src/mainboard/google/kahlee/mainboard.c
M src/mainboard/google/kahlee/mptable.c
M src/soc/amd/common/Makefile.inc
R src/soc/amd/common/block/include/amdblocks/amd_pci_util.h
A src/soc/amd/common/block/pci/Kconfig
A src/soc/amd/common/block/pci/Makefile.inc
R src/soc/amd/common/block/pci/amd_pci_util.c
A src/soc/amd/common/block/spi/Kconfig
A src/soc/amd/common/block/spi/Makefile.inc
R src/soc/amd/common/block/spi/spi.c
M src/soc/amd/stoneyridge/Kconfig
M src/soc/amd/stoneyridge/southbridge.c
14 files changed, 34 insertions(+), 10 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/22765/1
diff --git a/src/mainboard/amd/gardenia/mainboard.c b/src/mainboard/amd/gardenia/mainboard.c
index bd9f06c..25cf5b3 100644
--- a/src/mainboard/amd/gardenia/mainboard.c
+++ b/src/mainboard/amd/gardenia/mainboard.c
@@ -17,7 +17,7 @@
#include <device/device.h>
#include <arch/acpi.h>
#include <agesawrapper.h>
-#include <amd_pci_util.h>
+#include <amdblocks/amd_pci_util.h>
/***********************************************************
* These arrays set up the FCH PCI_INTR registers 0xC00/0xC01.
diff --git a/src/mainboard/amd/gardenia/mptable.c b/src/mainboard/amd/gardenia/mptable.c
index 5c07186..e29b3e3 100644
--- a/src/mainboard/amd/gardenia/mptable.c
+++ b/src/mainboard/amd/gardenia/mptable.c
@@ -23,7 +23,7 @@
#include <arch/cpu.h>
#include <cpu/x86/lapic.h>
#include <soc/southbridge.h>
-#include <amd_pci_util.h>
+#include <amdblocks/amd_pci_util.h>
static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned int length)
{
diff --git a/src/mainboard/google/kahlee/mainboard.c b/src/mainboard/google/kahlee/mainboard.c
index 8e0358a..fc13567 100644
--- a/src/mainboard/google/kahlee/mainboard.c
+++ b/src/mainboard/google/kahlee/mainboard.c
@@ -17,7 +17,7 @@
#include <device/device.h>
#include <arch/acpi.h>
#include <agesawrapper.h>
-#include <amd_pci_util.h>
+#include <amdblocks/amd_pci_util.h>
#include <cbmem.h>
#include <baseboard/variants.h>
#include <boardid.h>
diff --git a/src/mainboard/google/kahlee/mptable.c b/src/mainboard/google/kahlee/mptable.c
index 5c07186..e29b3e3 100644
--- a/src/mainboard/google/kahlee/mptable.c
+++ b/src/mainboard/google/kahlee/mptable.c
@@ -23,7 +23,7 @@
#include <arch/cpu.h>
#include <cpu/x86/lapic.h>
#include <soc/southbridge.h>
-#include <amd_pci_util.h>
+#include <amdblocks/amd_pci_util.h>
static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned int length)
{
diff --git a/src/soc/amd/common/Makefile.inc b/src/soc/amd/common/Makefile.inc
index aa27512..b485bb3 100644
--- a/src/soc/amd/common/Makefile.inc
+++ b/src/soc/amd/common/Makefile.inc
@@ -12,10 +12,8 @@
ramstage-y += agesawrapper.c
ramstage-y += amd_late_init.c
-ramstage-y += amd_pci_util.c
ramstage-y += def_callouts.c
ramstage-y += heapmanager.c
-ramstage-$(CONFIG_SPI_FLASH) += spi.c
subdirs-$(CONFIG_SOC_AMD_COMMON_BLOCK) += block
diff --git a/src/soc/amd/common/amd_pci_util.h b/src/soc/amd/common/block/include/amdblocks/amd_pci_util.h
similarity index 100%
rename from src/soc/amd/common/amd_pci_util.h
rename to src/soc/amd/common/block/include/amdblocks/amd_pci_util.h
diff --git a/src/soc/amd/common/block/pci/Kconfig b/src/soc/amd/common/block/pci/Kconfig
new file mode 100644
index 0000000..aa5e8db
--- /dev/null
+++ b/src/soc/amd/common/block/pci/Kconfig
@@ -0,0 +1,7 @@
+config SOC_AMD_COMMON_BLOCK_PCI
+ bool
+ default n
+ help
+ This option allows the SOC to use AMD common PCI utilities
+ to program IRQ. If this option is not used, the SOC must
+ implement these functions separately.
diff --git a/src/soc/amd/common/block/pci/Makefile.inc b/src/soc/amd/common/block/pci/Makefile.inc
new file mode 100644
index 0000000..fc40c9d
--- /dev/null
+++ b/src/soc/amd/common/block/pci/Makefile.inc
@@ -0,0 +1,5 @@
+ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_PCI),y)
+
+ramstage-y += amd_pci_util.c
+
+endif
diff --git a/src/soc/amd/common/amd_pci_util.c b/src/soc/amd/common/block/pci/amd_pci_util.c
similarity index 98%
rename from src/soc/amd/common/amd_pci_util.c
rename to src/soc/amd/common/block/pci/amd_pci_util.c
index 577b5cb..218f9d2 100644
--- a/src/soc/amd/common/amd_pci_util.c
+++ b/src/soc/amd/common/block/pci/amd_pci_util.c
@@ -17,7 +17,7 @@
#include <device/pci.h>
#include <arch/io.h>
#include <string.h>
-#include <amd_pci_util.h>
+#include <amdblocks/amd_pci_util.h>
#include <pc80/i8259.h>
#include <soc/amd_pci_int_defs.h>
#include <amd_pci_int_types.h>
@@ -174,7 +174,7 @@
continue;
} else if (pci_intr_idx >= FCH_INT_TABLE_SIZE) {
/* Index out of bounds */
- printk(BIOS_ERR, "%s: got 0xC00/0xC01 table index"
+ printk (BIOS_ERR, "%s: got 0xC00/0xC01 table index"
" 0x%x, max is 0x%x\n", __func__,
pci_intr_idx, FCH_INT_TABLE_SIZE);
continue;
diff --git a/src/soc/amd/common/block/spi/Kconfig b/src/soc/amd/common/block/spi/Kconfig
new file mode 100644
index 0000000..b594789
--- /dev/null
+++ b/src/soc/amd/common/block/spi/Kconfig
@@ -0,0 +1,7 @@
+config SOC_AMD_COMMON_BLOCK_SPI
+ bool
+ default n
+ help
+ This option allows the SOC to use AMD common PCI utilities
+ to program IRQ. If this option is not used, the SOC must
+ implement these functions separately.
diff --git a/src/soc/amd/common/block/spi/Makefile.inc b/src/soc/amd/common/block/spi/Makefile.inc
new file mode 100644
index 0000000..fe2eabc
--- /dev/null
+++ b/src/soc/amd/common/block/spi/Makefile.inc
@@ -0,0 +1,5 @@
+ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_SPI),y)
+
+ramstage-$(CONFIG_SPI_FLASH) += spi.c
+
+endif
diff --git a/src/soc/amd/common/spi.c b/src/soc/amd/common/block/spi/spi.c
similarity index 96%
rename from src/soc/amd/common/spi.c
rename to src/soc/amd/common/block/spi/spi.c
index 44c86e6..cf28985 100644
--- a/src/soc/amd/common/spi.c
+++ b/src/soc/amd/common/block/spi/spi.c
@@ -16,7 +16,7 @@
#include <console/console.h>
#include <spi-generic.h>
#include <spi_flash.h>
-#include "s3_resume.h"
+#include <amdblocks/s3_resume.h>
void spi_SaveS3info(u32 pos, u32 size, u8 *buf, u32 len)
{
diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig
index 3ca0e39..fe4e4ef 100644
--- a/src/soc/amd/stoneyridge/Kconfig
+++ b/src/soc/amd/stoneyridge/Kconfig
@@ -46,8 +46,10 @@
select SOC_AMD_PI
select SOC_AMD_COMMON
select SOC_AMD_COMMON_BLOCK
+ select SOC_AMD_COMMON_BLOCK_PCI
select SOC_AMD_COMMON_BLOCK_PSP
select SOC_AMD_COMMON_BLOCK_CAR
+ select SOC_AMD_COMMON_BLOCK_SPI
select C_ENVIRONMENT_BOOTBLOCK
select BOOTBLOCK_CONSOLE
select RELOCATABLE_MODULES
diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c
index dbf27bc..267b16b 100644
--- a/src/soc/amd/stoneyridge/southbridge.c
+++ b/src/soc/amd/stoneyridge/southbridge.c
@@ -24,7 +24,7 @@
#include <device/pci_ids.h>
#include <device/pci_ops.h>
#include <cbmem.h>
-#include <amd_pci_util.h>
+#include <amdblocks/amd_pci_util.h>
#include <soc/southbridge.h>
#include <soc/smi.h>
#include <fchec.h>
--
To view, visit https://review.coreboot.org/22765
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I3f965afa21124d4874d3b7bfe0f404a58b070e23
Gerrit-Change-Number: 22765
Gerrit-PatchSet: 1
Gerrit-Owner: Richard Spiegel <richard.spiegel at silverbackltd.com>
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