<p>Richard Spiegel has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/22765">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/amd/common: Move files to common/block<br><br>The following files need to be moved: amd_pci_util.c, amd_pci_util.h and<br>spi.c. The remaining files are AGESA related and will be part of a separate<br>issue/commit. After AGESA related files are moved, Kconfig and Makefile.inc<br>will be removed too, thus rending a clean soc/amd/common folder.<br><br>BUG=b:62240201<br>TEST=Build with no error.<br><br>Change-Id: I3f965afa21124d4874d3b7bfe0f404a58b070e23<br>Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com><br>---<br>M src/mainboard/amd/gardenia/mainboard.c<br>M src/mainboard/amd/gardenia/mptable.c<br>M src/mainboard/google/kahlee/mainboard.c<br>M src/mainboard/google/kahlee/mptable.c<br>M src/soc/amd/common/Makefile.inc<br>R src/soc/amd/common/block/include/amdblocks/amd_pci_util.h<br>A src/soc/amd/common/block/pci/Kconfig<br>A src/soc/amd/common/block/pci/Makefile.inc<br>R src/soc/amd/common/block/pci/amd_pci_util.c<br>A src/soc/amd/common/block/spi/Kconfig<br>A src/soc/amd/common/block/spi/Makefile.inc<br>R src/soc/amd/common/block/spi/spi.c<br>M src/soc/amd/stoneyridge/Kconfig<br>M src/soc/amd/stoneyridge/southbridge.c<br>14 files changed, 34 insertions(+), 10 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/22765/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/mainboard/amd/gardenia/mainboard.c b/src/mainboard/amd/gardenia/mainboard.c<br>index bd9f06c..25cf5b3 100644<br>--- a/src/mainboard/amd/gardenia/mainboard.c<br>+++ b/src/mainboard/amd/gardenia/mainboard.c<br>@@ -17,7 +17,7 @@<br> #include <device/device.h><br> #include <arch/acpi.h><br> #include <agesawrapper.h><br>-#include <amd_pci_util.h><br>+#include <amdblocks/amd_pci_util.h><br> <br> /***********************************************************<br> * These arrays set up the FCH PCI_INTR registers 0xC00/0xC01.<br>diff --git a/src/mainboard/amd/gardenia/mptable.c b/src/mainboard/amd/gardenia/mptable.c<br>index 5c07186..e29b3e3 100644<br>--- a/src/mainboard/amd/gardenia/mptable.c<br>+++ b/src/mainboard/amd/gardenia/mptable.c<br>@@ -23,7 +23,7 @@<br> #include <arch/cpu.h><br> #include <cpu/x86/lapic.h><br> #include <soc/southbridge.h><br>-#include <amd_pci_util.h><br>+#include <amdblocks/amd_pci_util.h><br> <br> static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned int length)<br> {<br>diff --git a/src/mainboard/google/kahlee/mainboard.c b/src/mainboard/google/kahlee/mainboard.c<br>index 8e0358a..fc13567 100644<br>--- a/src/mainboard/google/kahlee/mainboard.c<br>+++ b/src/mainboard/google/kahlee/mainboard.c<br>@@ -17,7 +17,7 @@<br> #include <device/device.h><br> #include <arch/acpi.h><br> #include <agesawrapper.h><br>-#include <amd_pci_util.h><br>+#include <amdblocks/amd_pci_util.h><br> #include <cbmem.h><br> #include <baseboard/variants.h><br> #include <boardid.h><br>diff --git a/src/mainboard/google/kahlee/mptable.c b/src/mainboard/google/kahlee/mptable.c<br>index 5c07186..e29b3e3 100644<br>--- a/src/mainboard/google/kahlee/mptable.c<br>+++ b/src/mainboard/google/kahlee/mptable.c<br>@@ -23,7 +23,7 @@<br> #include <arch/cpu.h><br> #include <cpu/x86/lapic.h><br> #include <soc/southbridge.h><br>-#include <amd_pci_util.h><br>+#include <amdblocks/amd_pci_util.h><br> <br> static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned int length)<br> {<br>diff --git a/src/soc/amd/common/Makefile.inc b/src/soc/amd/common/Makefile.inc<br>index aa27512..b485bb3 100644<br>--- a/src/soc/amd/common/Makefile.inc<br>+++ b/src/soc/amd/common/Makefile.inc<br>@@ -12,10 +12,8 @@<br> <br> ramstage-y += agesawrapper.c<br> ramstage-y += amd_late_init.c<br>-ramstage-y += amd_pci_util.c<br> ramstage-y += def_callouts.c<br> ramstage-y += heapmanager.c<br>-ramstage-$(CONFIG_SPI_FLASH) += spi.c<br> <br> subdirs-$(CONFIG_SOC_AMD_COMMON_BLOCK) += block<br> <br>diff --git a/src/soc/amd/common/amd_pci_util.h b/src/soc/amd/common/block/include/amdblocks/amd_pci_util.h<br>similarity index 100%<br>rename from src/soc/amd/common/amd_pci_util.h<br>rename to src/soc/amd/common/block/include/amdblocks/amd_pci_util.h<br>diff --git a/src/soc/amd/common/block/pci/Kconfig b/src/soc/amd/common/block/pci/Kconfig<br>new file mode 100644<br>index 0000000..aa5e8db<br>--- /dev/null<br>+++ b/src/soc/amd/common/block/pci/Kconfig<br>@@ -0,0 +1,7 @@<br>+config SOC_AMD_COMMON_BLOCK_PCI<br>+ bool<br>+ default n<br>+ help<br>+ This option allows the SOC to use AMD common PCI utilities<br>+ to program IRQ. If this option is not used, the SOC must<br>+ implement these functions separately.<br>diff --git a/src/soc/amd/common/block/pci/Makefile.inc b/src/soc/amd/common/block/pci/Makefile.inc<br>new file mode 100644<br>index 0000000..fc40c9d<br>--- /dev/null<br>+++ b/src/soc/amd/common/block/pci/Makefile.inc<br>@@ -0,0 +1,5 @@<br>+ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_PCI),y)<br>+<br>+ramstage-y += amd_pci_util.c<br>+<br>+endif<br>diff --git a/src/soc/amd/common/amd_pci_util.c b/src/soc/amd/common/block/pci/amd_pci_util.c<br>similarity index 98%<br>rename from src/soc/amd/common/amd_pci_util.c<br>rename to src/soc/amd/common/block/pci/amd_pci_util.c<br>index 577b5cb..218f9d2 100644<br>--- a/src/soc/amd/common/amd_pci_util.c<br>+++ b/src/soc/amd/common/block/pci/amd_pci_util.c<br>@@ -17,7 +17,7 @@<br> #include <device/pci.h><br> #include <arch/io.h><br> #include <string.h><br>-#include <amd_pci_util.h><br>+#include <amdblocks/amd_pci_util.h><br> #include <pc80/i8259.h><br> #include <soc/amd_pci_int_defs.h><br> #include <amd_pci_int_types.h><br>@@ -174,7 +174,7 @@<br> continue;<br> } else if (pci_intr_idx >= FCH_INT_TABLE_SIZE) {<br> /* Index out of bounds */<br>- printk(BIOS_ERR, "%s: got 0xC00/0xC01 table index"<br>+ printk (BIOS_ERR, "%s: got 0xC00/0xC01 table index"<br> " 0x%x, max is 0x%x\n", __func__,<br> pci_intr_idx, FCH_INT_TABLE_SIZE);<br> continue;<br>diff --git a/src/soc/amd/common/block/spi/Kconfig b/src/soc/amd/common/block/spi/Kconfig<br>new file mode 100644<br>index 0000000..b594789<br>--- /dev/null<br>+++ b/src/soc/amd/common/block/spi/Kconfig<br>@@ -0,0 +1,7 @@<br>+config SOC_AMD_COMMON_BLOCK_SPI<br>+ bool<br>+ default n<br>+ help<br>+ This option allows the SOC to use AMD common PCI utilities<br>+ to program IRQ. If this option is not used, the SOC must<br>+ implement these functions separately.<br>diff --git a/src/soc/amd/common/block/spi/Makefile.inc b/src/soc/amd/common/block/spi/Makefile.inc<br>new file mode 100644<br>index 0000000..fe2eabc<br>--- /dev/null<br>+++ b/src/soc/amd/common/block/spi/Makefile.inc<br>@@ -0,0 +1,5 @@<br>+ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_SPI),y)<br>+<br>+ramstage-$(CONFIG_SPI_FLASH) += spi.c<br>+<br>+endif<br>diff --git a/src/soc/amd/common/spi.c b/src/soc/amd/common/block/spi/spi.c<br>similarity index 96%<br>rename from src/soc/amd/common/spi.c<br>rename to src/soc/amd/common/block/spi/spi.c<br>index 44c86e6..cf28985 100644<br>--- a/src/soc/amd/common/spi.c<br>+++ b/src/soc/amd/common/block/spi/spi.c<br>@@ -16,7 +16,7 @@<br> #include <console/console.h><br> #include <spi-generic.h><br> #include <spi_flash.h><br>-#include "s3_resume.h"<br>+#include <amdblocks/s3_resume.h><br> <br> void spi_SaveS3info(u32 pos, u32 size, u8 *buf, u32 len)<br> {<br>diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig<br>index 3ca0e39..fe4e4ef 100644<br>--- a/src/soc/amd/stoneyridge/Kconfig<br>+++ b/src/soc/amd/stoneyridge/Kconfig<br>@@ -46,8 +46,10 @@<br> select SOC_AMD_PI<br> select SOC_AMD_COMMON<br> select SOC_AMD_COMMON_BLOCK<br>+ select SOC_AMD_COMMON_BLOCK_PCI<br> select SOC_AMD_COMMON_BLOCK_PSP<br> select SOC_AMD_COMMON_BLOCK_CAR<br>+ select SOC_AMD_COMMON_BLOCK_SPI<br> select C_ENVIRONMENT_BOOTBLOCK<br> select BOOTBLOCK_CONSOLE<br> select RELOCATABLE_MODULES<br>diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c<br>index dbf27bc..267b16b 100644<br>--- a/src/soc/amd/stoneyridge/southbridge.c<br>+++ b/src/soc/amd/stoneyridge/southbridge.c<br>@@ -24,7 +24,7 @@<br> #include <device/pci_ids.h><br> #include <device/pci_ops.h><br> #include <cbmem.h><br>-#include <amd_pci_util.h><br>+#include <amdblocks/amd_pci_util.h><br> #include <soc/southbridge.h><br> #include <soc/smi.h><br> #include <fchec.h><br></pre><p>To view, visit <a href="https://review.coreboot.org/22765">change 22765</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/22765"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I3f965afa21124d4874d3b7bfe0f404a58b070e23 </div>
<div style="display:none"> Gerrit-Change-Number: 22765 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Richard Spiegel <richard.spiegel@silverbackltd.com> </div>