[coreboot-gerrit] Change in coreboot[master]: soc/intel/apollolake: Add SMI and SCI support for ESPI

[Shaunak Saha (Code Review)]

Shaunak Saha has uploaded this change for review. ( https://review.coreboot.org/22758


Change subject: soc/intel/apollolake: Add SMI and SCI support for ESPI
......................................................................

soc/intel/apollolake: Add SMI and SCI support for ESPI

This patch adds the SMI bits for SMI_EN, SMI_STS and GPE
register in pm.h. The southbridge handler for espi smi is
also added. In gpe.h we add GPE0_ESPI which is bit 20 in
GPE0a_EN and enables the setting of the ESPI_SCI STS bit
to generate a wake event and/or an SCI or SMI.

TEST=  Boot to OS.

Change-Id: I2b8372ffbe0949ddd4aa83bdd7c0a01ade3ed40e
Signed-off-by: Shaunak Saha <shaunak.saha at intel.com>
---
M src/soc/intel/apollolake/include/soc/gpe.h
M src/soc/intel/apollolake/include/soc/pm.h
M src/soc/intel/apollolake/smihandler.c
3 files changed, 24 insertions(+), 0 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/22758/1

diff --git a/src/soc/intel/apollolake/include/soc/gpe.h b/src/soc/intel/apollolake/include/soc/gpe.h
index 7dfb6f5..e1ebd96 100644
--- a/src/soc/intel/apollolake/include/soc/gpe.h
+++ b/src/soc/intel/apollolake/include/soc/gpe.h
@@ -136,5 +136,8 @@
 #define GPE0_DW3_30		126
 #define GPE0_DW3_31		127
 
+#if IS_ENABLED(CONFIG_SOC_INTEL_GLK)
+#define GPE0_ESPI               20
+#endif
 #define GPE_MAX			GPE0_DW3_31
 #endif
diff --git a/src/soc/intel/apollolake/include/soc/pm.h b/src/soc/intel/apollolake/include/soc/pm.h
index 37e4ced..85c7678 100644
--- a/src/soc/intel/apollolake/include/soc/pm.h
+++ b/src/soc/intel/apollolake/include/soc/pm.h
@@ -47,6 +47,9 @@
 
 #define SMI_EN			0x40
 
+#if IS_ENABLED(CONFIG_SOC_INTEL_GLK)
+#define SMI_ESPI		28
+#endif
 #define SMI_OCP_CSE		27
 #define SMI_SPI			26
 #define SMI_SPI_SSMI		25
@@ -71,6 +74,9 @@
 #define SMI_EOS			1
 #define SMI_GBL			0
 
+#if IS_ENABLED(CONFIG_SOC_INTEL_GLK)
+#define   ESPI_SMI_EN	(1 << SMI_ESPI)
+#endif
 #define   USB_EN	(1 << SMI_XHCI) /* Legacy USB2 SMI logic */
 #define   PERIODIC_EN	(1 << SMI_PERIODIC) /* SMI on PERIODIC_STS in SMI_STS */
 #define   TCO_EN	(1 << SMI_TCO) /* Enable TCO Logic (BIOSWE et al) */
@@ -96,11 +102,19 @@
  *  - on microcontroller writes (io 0x62/0x66)
  *  - on TCO events
  */
+#if IS_ENABLED(CONFIG_SOC_INTEL_GLK)
+#define   ENABLE_SMI_PARAMS \
+	(ESPI_SMI_EN | APMC_EN | SLP_SMI_EN | GBL_SMI_EN | EOS | GPIO_EN)
+#else
 #define   ENABLE_SMI_PARAMS \
 	(APMC_EN | SLP_SMI_EN | GBL_SMI_EN | EOS | GPIO_EN)
+#endif
 
 #define SMI_STS			0x44
 /* Bits for SMI status */
+#if IS_ENABLED(CONFIG_SOC_INTEL_GLK)
+#define  ESPI_SMI_STS_BIT	28
+#endif
 #define  PMC_OCP_SMI_STS	27
 #define  SPI_SMI_STS		26
 #define  SPI_SSMI_STS		25
@@ -138,6 +152,9 @@
 #define  GPE0_C			2
 #define  GPE0_D			3
 #define GPE_STD			GPE0_A
+#if IS_ENABLED(CONFIG_SOC_INTEL_GLK)
+#define   ESPI_STS              (1 << 20)
+#endif
 #define   SATA_PME_STS		(1 << 17)
 #define   SMB_WAK_STS		(1 << 16)
 #define   AVS_PME_STS		(1 << 14)
@@ -148,6 +165,9 @@
 #define   PCIE_GPE_STS		(1 << 9)
 #define   SWGPE_STS		(1 << 2)
 #define GPE0_EN(x)		(0x30 + (x * 4))
+#if IS_ENABLED(CONFIG_SOC_INTEL_GLK)
+#define   ESPI_EN		(1 << 20)
+#endif
 #define   SATA_PME_EN		(1 << 17)
 #define   SMB_WAK_EN		(1 << 16)
 #define   AVS_PME_EN		(1 << 14)
diff --git a/src/soc/intel/apollolake/smihandler.c b/src/soc/intel/apollolake/smihandler.c
index 22c7930..1182090 100644
--- a/src/soc/intel/apollolake/smihandler.c
+++ b/src/soc/intel/apollolake/smihandler.c
@@ -41,4 +41,5 @@
 	[GPIO_SMI_STS] = smihandler_southbridge_gpi,
 	[TCO_SMI_STS] = smihandler_southbridge_tco,
 	[PERIODIC_SMI_STS] = smihandler_southbridge_periodic,
+	[ESPI_SMI_STS_BIT] = smihandler_southbridge_espi,
 };

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I2b8372ffbe0949ddd4aa83bdd7c0a01ade3ed40e
Gerrit-Change-Number: 22758
Gerrit-PatchSet: 1
Gerrit-Owner: Shaunak Saha <shaunak.saha at intel.com>
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