<p>Shaunak Saha has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/22758">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/intel/apollolake: Add SMI and SCI support for ESPI<br><br>This patch adds the SMI bits for SMI_EN, SMI_STS and GPE<br>register in pm.h. The southbridge handler for espi smi is<br>also added. In gpe.h we add GPE0_ESPI which is bit 20 in<br>GPE0a_EN and enables the setting of the ESPI_SCI STS bit<br>to generate a wake event and/or an SCI or SMI.<br><br>TEST= Boot to OS.<br><br>Change-Id: I2b8372ffbe0949ddd4aa83bdd7c0a01ade3ed40e<br>Signed-off-by: Shaunak Saha <shaunak.saha@intel.com><br>---<br>M src/soc/intel/apollolake/include/soc/gpe.h<br>M src/soc/intel/apollolake/include/soc/pm.h<br>M src/soc/intel/apollolake/smihandler.c<br>3 files changed, 24 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/22758/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/soc/intel/apollolake/include/soc/gpe.h b/src/soc/intel/apollolake/include/soc/gpe.h<br>index 7dfb6f5..e1ebd96 100644<br>--- a/src/soc/intel/apollolake/include/soc/gpe.h<br>+++ b/src/soc/intel/apollolake/include/soc/gpe.h<br>@@ -136,5 +136,8 @@<br> #define GPE0_DW3_30 126<br> #define GPE0_DW3_31 127<br> <br>+#if IS_ENABLED(CONFIG_SOC_INTEL_GLK)<br>+#define GPE0_ESPI 20<br>+#endif<br> #define GPE_MAX GPE0_DW3_31<br> #endif<br>diff --git a/src/soc/intel/apollolake/include/soc/pm.h b/src/soc/intel/apollolake/include/soc/pm.h<br>index 37e4ced..85c7678 100644<br>--- a/src/soc/intel/apollolake/include/soc/pm.h<br>+++ b/src/soc/intel/apollolake/include/soc/pm.h<br>@@ -47,6 +47,9 @@<br> <br> #define SMI_EN 0x40<br> <br>+#if IS_ENABLED(CONFIG_SOC_INTEL_GLK)<br>+#define SMI_ESPI 28<br>+#endif<br> #define SMI_OCP_CSE 27<br> #define SMI_SPI 26<br> #define SMI_SPI_SSMI 25<br>@@ -71,6 +74,9 @@<br> #define SMI_EOS 1<br> #define SMI_GBL 0<br> <br>+#if IS_ENABLED(CONFIG_SOC_INTEL_GLK)<br>+#define ESPI_SMI_EN (1 << SMI_ESPI)<br>+#endif<br> #define USB_EN (1 << SMI_XHCI) /* Legacy USB2 SMI logic */<br> #define PERIODIC_EN (1 << SMI_PERIODIC) /* SMI on PERIODIC_STS in SMI_STS */<br> #define TCO_EN (1 << SMI_TCO) /* Enable TCO Logic (BIOSWE et al) */<br>@@ -96,11 +102,19 @@<br> * - on microcontroller writes (io 0x62/0x66)<br> * - on TCO events<br> */<br>+#if IS_ENABLED(CONFIG_SOC_INTEL_GLK)<br>+#define ENABLE_SMI_PARAMS \<br>+ (ESPI_SMI_EN | APMC_EN | SLP_SMI_EN | GBL_SMI_EN | EOS | GPIO_EN)<br>+#else<br> #define ENABLE_SMI_PARAMS \<br> (APMC_EN | SLP_SMI_EN | GBL_SMI_EN | EOS | GPIO_EN)<br>+#endif<br> <br> #define SMI_STS 0x44<br> /* Bits for SMI status */<br>+#if IS_ENABLED(CONFIG_SOC_INTEL_GLK)<br>+#define ESPI_SMI_STS_BIT 28<br>+#endif<br> #define PMC_OCP_SMI_STS 27<br> #define SPI_SMI_STS 26<br> #define SPI_SSMI_STS 25<br>@@ -138,6 +152,9 @@<br> #define GPE0_C 2<br> #define GPE0_D 3<br> #define GPE_STD GPE0_A<br>+#if IS_ENABLED(CONFIG_SOC_INTEL_GLK)<br>+#define ESPI_STS (1 << 20)<br>+#endif<br> #define SATA_PME_STS (1 << 17)<br> #define SMB_WAK_STS (1 << 16)<br> #define AVS_PME_STS (1 << 14)<br>@@ -148,6 +165,9 @@<br> #define PCIE_GPE_STS (1 << 9)<br> #define SWGPE_STS (1 << 2)<br> #define GPE0_EN(x) (0x30 + (x * 4))<br>+#if IS_ENABLED(CONFIG_SOC_INTEL_GLK)<br>+#define ESPI_EN (1 << 20)<br>+#endif<br> #define SATA_PME_EN (1 << 17)<br> #define SMB_WAK_EN (1 << 16)<br> #define AVS_PME_EN (1 << 14)<br>diff --git a/src/soc/intel/apollolake/smihandler.c b/src/soc/intel/apollolake/smihandler.c<br>index 22c7930..1182090 100644<br>--- a/src/soc/intel/apollolake/smihandler.c<br>+++ b/src/soc/intel/apollolake/smihandler.c<br>@@ -41,4 +41,5 @@<br> [GPIO_SMI_STS] = smihandler_southbridge_gpi,<br> [TCO_SMI_STS] = smihandler_southbridge_tco,<br> [PERIODIC_SMI_STS] = smihandler_southbridge_periodic,<br>+ [ESPI_SMI_STS_BIT] = smihandler_southbridge_espi,<br> };<br></pre><p>To view, visit <a href="https://review.coreboot.org/22758">change 22758</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/22758"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I2b8372ffbe0949ddd4aa83bdd7c0a01ade3ed40e </div>
<div style="display:none"> Gerrit-Change-Number: 22758 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Shaunak Saha <shaunak.saha@intel.com> </div>