[coreboot-gerrit] Change in coreboot[master]: soc/intel/skylake: Clean up bootblock/report_platform.c
Subrata Banik (Code Review)
gerrit at coreboot.org
Wed Dec 6 14:44:01 CET 2017
Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/22756
Change subject: soc/intel/skylake: Clean up bootblock/report_platform.c
......................................................................
soc/intel/skylake: Clean up bootblock/report_platform.c
This patch ensures that all required information for
pch/mch/igd deviceid and revision available in single
stage and make use of local references.
TEST=Build and boot soraka/eve
Change-Id: I6f7f219536831210750a486ee3b3308d6f285451
Signed-off-by: Subrata Banik <subrata.banik at intel.com>
---
M src/soc/intel/skylake/Makefile.inc
M src/soc/intel/skylake/bootblock/report_platform.c
M src/soc/intel/skylake/include/soc/pch.h
D src/soc/intel/skylake/pch.c
4 files changed, 19 insertions(+), 45 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/22756/1
diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc
index c40f6e1..7fc91c8 100644
--- a/src/soc/intel/skylake/Makefile.inc
+++ b/src/soc/intel/skylake/Makefile.inc
@@ -18,13 +18,11 @@
bootblock-$(CONFIG_UART_DEBUG) += uart_debug.c
bootblock-y += gpio.c
bootblock-y += gspi.c
-bootblock-y += pch.c
bootblock-y += pmutil.c
bootblock-y += spi.c
bootblock-y += lpc.c
verstage-y += gspi.c
-verstage-y += pch.c
verstage-$(CONFIG_UART_DEBUG) += uart_debug.c
verstage-y += pmutil.c
verstage-y += i2c.c
@@ -35,7 +33,6 @@
romstage-y += i2c.c
romstage-y += memmap.c
romstage-y += me.c
-romstage-y += pch.c
romstage-y += pei_data.c
romstage-y += pmc.c
romstage-y += pmutil.c
@@ -58,7 +55,6 @@
ramstage-y += lpc.c
ramstage-y += me.c
ramstage-y += memmap.c
-ramstage-y += pch.c
ramstage-y += pei_data.c
ramstage-y += pmc.c
ramstage-y += pmutil.c
@@ -75,7 +71,6 @@
smm-y += elog.c
smm-y += gpio.c
-smm-y += pch.c
smm-y += pmutil.c
smm-y += smihandler.c
smm-$(CONFIG_UART_DEBUG) += uart_debug.c
diff --git a/src/soc/intel/skylake/bootblock/report_platform.c b/src/soc/intel/skylake/bootblock/report_platform.c
index 69484fb..9be2e40 100644
--- a/src/soc/intel/skylake/bootblock/report_platform.c
+++ b/src/soc/intel/skylake/bootblock/report_platform.c
@@ -96,6 +96,16 @@
{ PCI_DEVICE_ID_INTEL_KBL_GT2_SHALM, "Kabylake HALO GT2" },
};
+static uint8_t get_dev_revision(device_t dev)
+{
+ return pci_read_config8(dev, PCI_REVISION_ID);
+}
+
+static uint16_t get_dev_id(device_t dev)
+{
+ return pci_read_config16(dev, PCI_DEVICE_ID);
+}
+
static void report_cpu_info(void)
{
struct cpuid_result cpuidr;
@@ -153,8 +163,9 @@
static void report_mch_info(void)
{
int i;
- u16 mchid = pci_read_config16(SA_DEV_ROOT, PCI_DEVICE_ID);
- u8 mch_revision = pci_read_config8(SA_DEV_ROOT, PCI_REVISION_ID);
+ device_t dev = SA_DEV_ROOT;
+ uint16_t mchid = get_dev_id(dev);
+ uint8_t mch_revision = get_dev_revision(dev);
const char *mch_type = "Unknown";
for (i = 0; i < ARRAY_SIZE(mch_table); i++) {
@@ -171,7 +182,8 @@
static void report_pch_info(void)
{
int i;
- u16 lpcid = pch_type();
+ device_t dev = PCH_DEV_LPC;
+ uint16_t lpcid = get_dev_id(dev);
const char *pch_type = "Unknown";
for (i = 0; i < ARRAY_SIZE(pch_table); i++) {
@@ -181,13 +193,14 @@
}
}
printk(BIOS_DEBUG, "PCH: device id %04x (rev %02x) is %s\n",
- lpcid, pch_revision(), pch_type);
+ lpcid, get_dev_revision(dev), pch_type);
}
static void report_igd_info(void)
{
int i;
- u16 igdid = pci_read_config16(SA_DEV_IGD, PCI_DEVICE_ID);
+ device_t dev = SA_DEV_IGD;
+ uint16_t igdid = get_dev_id(dev);
const char *igd_type = "Unknown";
for (i = 0; i < ARRAY_SIZE(igd_table); i++) {
@@ -197,7 +210,7 @@
}
}
printk(BIOS_DEBUG, "IGD: device id %04x (rev %02x) is %s\n",
- igdid, pci_read_config8(SA_DEV_IGD, PCI_REVISION_ID), igd_type);
+ igdid, get_dev_revision(dev), igd_type);
}
void report_platform_info(void)
diff --git a/src/soc/intel/skylake/include/soc/pch.h b/src/soc/intel/skylake/include/soc/pch.h
index 800e0de..18b030d 100644
--- a/src/soc/intel/skylake/include/soc/pch.h
+++ b/src/soc/intel/skylake/include/soc/pch.h
@@ -21,8 +21,6 @@
#include <device/device.h>
#include <rules.h>
-u8 pch_revision(void);
-u16 pch_type(void);
void pch_log_state(void);
#if ENV_RAMSTAGE
void pch_disable_devfn(device_t dev);
diff --git a/src/soc/intel/skylake/pch.c b/src/soc/intel/skylake/pch.c
deleted file mode 100644
index 451bebb..0000000
--- a/src/soc/intel/skylake/pch.c
+++ /dev/null
@@ -1,32 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008-2009 coresystems GmbH
- * Copyright (C) 2014 Google Inc.
- * Copyright (C) 2015 Intel Corporation.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <arch/io.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <soc/pch.h>
-#include <soc/pci_devs.h>
-
-u8 pch_revision(void)
-{
- return pci_read_config8(PCH_DEV_LPC, PCI_REVISION_ID);
-}
-
-u16 pch_type(void)
-{
- return pci_read_config16(PCH_DEV_LPC, PCI_DEVICE_ID);
-}
--
To view, visit https://review.coreboot.org/22756
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I6f7f219536831210750a486ee3b3308d6f285451
Gerrit-Change-Number: 22756
Gerrit-PatchSet: 1
Gerrit-Owner: Subrata Banik <subrata.banik at intel.com>
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