<p>Subrata Banik has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/22756">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/intel/skylake: Clean up bootblock/report_platform.c<br><br>This patch ensures that all required information for<br>pch/mch/igd deviceid and revision available in single<br>stage and make use of local references.<br><br>TEST=Build and boot soraka/eve<br><br>Change-Id: I6f7f219536831210750a486ee3b3308d6f285451<br>Signed-off-by: Subrata Banik <subrata.banik@intel.com><br>---<br>M src/soc/intel/skylake/Makefile.inc<br>M src/soc/intel/skylake/bootblock/report_platform.c<br>M src/soc/intel/skylake/include/soc/pch.h<br>D src/soc/intel/skylake/pch.c<br>4 files changed, 19 insertions(+), 45 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/22756/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc<br>index c40f6e1..7fc91c8 100644<br>--- a/src/soc/intel/skylake/Makefile.inc<br>+++ b/src/soc/intel/skylake/Makefile.inc<br>@@ -18,13 +18,11 @@<br> bootblock-$(CONFIG_UART_DEBUG) += uart_debug.c<br> bootblock-y += gpio.c<br> bootblock-y += gspi.c<br>-bootblock-y += pch.c<br> bootblock-y += pmutil.c<br> bootblock-y += spi.c<br> bootblock-y += lpc.c<br> <br> verstage-y += gspi.c<br>-verstage-y += pch.c<br> verstage-$(CONFIG_UART_DEBUG) += uart_debug.c<br> verstage-y += pmutil.c<br> verstage-y += i2c.c<br>@@ -35,7 +33,6 @@<br> romstage-y += i2c.c<br> romstage-y += memmap.c<br> romstage-y += me.c<br>-romstage-y += pch.c<br> romstage-y += pei_data.c<br> romstage-y += pmc.c<br> romstage-y += pmutil.c<br>@@ -58,7 +55,6 @@<br> ramstage-y += lpc.c<br> ramstage-y += me.c<br> ramstage-y += memmap.c<br>-ramstage-y += pch.c<br> ramstage-y += pei_data.c<br> ramstage-y += pmc.c<br> ramstage-y += pmutil.c<br>@@ -75,7 +71,6 @@<br> <br> smm-y += elog.c<br> smm-y += gpio.c<br>-smm-y += pch.c<br> smm-y += pmutil.c<br> smm-y += smihandler.c<br> smm-$(CONFIG_UART_DEBUG) += uart_debug.c<br>diff --git a/src/soc/intel/skylake/bootblock/report_platform.c b/src/soc/intel/skylake/bootblock/report_platform.c<br>index 69484fb..9be2e40 100644<br>--- a/src/soc/intel/skylake/bootblock/report_platform.c<br>+++ b/src/soc/intel/skylake/bootblock/report_platform.c<br>@@ -96,6 +96,16 @@<br> { PCI_DEVICE_ID_INTEL_KBL_GT2_SHALM, "Kabylake HALO GT2" },<br> };<br> <br>+static uint8_t get_dev_revision(device_t dev)<br>+{<br>+ return pci_read_config8(dev, PCI_REVISION_ID);<br>+}<br>+<br>+static uint16_t get_dev_id(device_t dev)<br>+{<br>+ return pci_read_config16(dev, PCI_DEVICE_ID);<br>+}<br>+<br> static void report_cpu_info(void)<br> {<br> struct cpuid_result cpuidr;<br>@@ -153,8 +163,9 @@<br> static void report_mch_info(void)<br> {<br> int i;<br>- u16 mchid = pci_read_config16(SA_DEV_ROOT, PCI_DEVICE_ID);<br>- u8 mch_revision = pci_read_config8(SA_DEV_ROOT, PCI_REVISION_ID);<br>+ device_t dev = SA_DEV_ROOT;<br>+ uint16_t mchid = get_dev_id(dev);<br>+ uint8_t mch_revision = get_dev_revision(dev);<br> const char *mch_type = "Unknown";<br> <br> for (i = 0; i < ARRAY_SIZE(mch_table); i++) {<br>@@ -171,7 +182,8 @@<br> static void report_pch_info(void)<br> {<br> int i;<br>- u16 lpcid = pch_type();<br>+ device_t dev = PCH_DEV_LPC;<br>+ uint16_t lpcid = get_dev_id(dev);<br> const char *pch_type = "Unknown";<br> <br> for (i = 0; i < ARRAY_SIZE(pch_table); i++) {<br>@@ -181,13 +193,14 @@<br> }<br> }<br> printk(BIOS_DEBUG, "PCH: device id %04x (rev %02x) is %s\n",<br>- lpcid, pch_revision(), pch_type);<br>+ lpcid, get_dev_revision(dev), pch_type);<br> }<br> <br> static void report_igd_info(void)<br> {<br> int i;<br>- u16 igdid = pci_read_config16(SA_DEV_IGD, PCI_DEVICE_ID);<br>+ device_t dev = SA_DEV_IGD;<br>+ uint16_t igdid = get_dev_id(dev);<br> const char *igd_type = "Unknown";<br> <br> for (i = 0; i < ARRAY_SIZE(igd_table); i++) {<br>@@ -197,7 +210,7 @@<br> }<br> }<br> printk(BIOS_DEBUG, "IGD: device id %04x (rev %02x) is %s\n",<br>- igdid, pci_read_config8(SA_DEV_IGD, PCI_REVISION_ID), igd_type);<br>+ igdid, get_dev_revision(dev), igd_type);<br> }<br> <br> void report_platform_info(void)<br>diff --git a/src/soc/intel/skylake/include/soc/pch.h b/src/soc/intel/skylake/include/soc/pch.h<br>index 800e0de..18b030d 100644<br>--- a/src/soc/intel/skylake/include/soc/pch.h<br>+++ b/src/soc/intel/skylake/include/soc/pch.h<br>@@ -21,8 +21,6 @@<br> #include <device/device.h><br> #include <rules.h><br> <br>-u8 pch_revision(void);<br>-u16 pch_type(void);<br> void pch_log_state(void);<br> #if ENV_RAMSTAGE<br> void pch_disable_devfn(device_t dev);<br>diff --git a/src/soc/intel/skylake/pch.c b/src/soc/intel/skylake/pch.c<br>deleted file mode 100644<br>index 451bebb..0000000<br>--- a/src/soc/intel/skylake/pch.c<br>+++ /dev/null<br>@@ -1,32 +0,0 @@<br>-/*<br>- * This file is part of the coreboot project.<br>- *<br>- * Copyright (C) 2008-2009 coresystems GmbH<br>- * Copyright (C) 2014 Google Inc.<br>- * Copyright (C) 2015 Intel Corporation.<br>- *<br>- * This program is free software; you can redistribute it and/or modify<br>- * it under the terms of the GNU General Public License as published by<br>- * the Free Software Foundation; version 2 of the License.<br>- *<br>- * This program is distributed in the hope that it will be useful,<br>- * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>- * GNU General Public License for more details.<br>- */<br>-<br>-#include <arch/io.h><br>-#include <device/device.h><br>-#include <device/pci.h><br>-#include <soc/pch.h><br>-#include <soc/pci_devs.h><br>-<br>-u8 pch_revision(void)<br>-{<br>- return pci_read_config8(PCH_DEV_LPC, PCI_REVISION_ID);<br>-}<br>-<br>-u16 pch_type(void)<br>-{<br>- return pci_read_config16(PCH_DEV_LPC, PCI_DEVICE_ID);<br>-}<br></pre><p>To view, visit <a href="https://review.coreboot.org/22756">change 22756</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/22756"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I6f7f219536831210750a486ee3b3308d6f285451 </div>
<div style="display:none"> Gerrit-Change-Number: 22756 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Subrata Banik <subrata.banik@intel.com> </div>