[coreboot-gerrit] Change in coreboot[master]: soc/intel/apollolake: Clean up UART code
Aamir Bohra (Code Review)
gerrit at coreboot.org
Wed Dec 6 14:32:50 CET 2017
Aamir Bohra has uploaded this change for review. ( https://review.coreboot.org/22754
Change subject: soc/intel/apollolake: Clean up UART code
......................................................................
soc/intel/apollolake: Clean up UART code
Clean up and move UART related code under a single uart.c file.
Change-Id: I9a30258ba43ee5920f585c1bd06bc25773778ec4
Signed-off-by: Aamir Bohra <aamir.bohra at intel.com>
---
M src/soc/intel/apollolake/Makefile.inc
M src/soc/intel/apollolake/uart.c
D src/soc/intel/apollolake/uart_early.c
3 files changed, 61 insertions(+), 83 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/22754/1
diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc
index 60f4ee3..68f2947 100644
--- a/src/soc/intel/apollolake/Makefile.inc
+++ b/src/soc/intel/apollolake/Makefile.inc
@@ -16,14 +16,14 @@
bootblock-y += mmap_boot.c
bootblock-y += pmutil.c
bootblock-y += spi.c
-bootblock-$(CONFIG_SOC_UART_DEBUG) += uart_early.c
+bootblock-$(CONFIG_SOC_UART_DEBUG) += uart.c
bootblock-$(CONFIG_FSP_CAR) += bootblock/cache_as_ram_fsp.S
romstage-y += car.c
romstage-$(CONFIG_PLATFORM_USES_FSP2_0) += romstage.c
romstage-y += heci.c
romstage-y += i2c.c
-romstage-$(CONFIG_SOC_UART_DEBUG) += uart_early.c
+romstage-$(CONFIG_SOC_UART_DEBUG) += uart.c
romstage-y += memmap.c
romstage-y += meminit.c
ifeq ($(CONFIG_SOC_INTEL_GLK),y)
@@ -40,8 +40,7 @@
smm-y += pmutil.c
smm-y += smihandler.c
smm-y += spi.c
-smm-y += uart_early.c
-smm-y += uart.c
+smm-$(CONFIG_SOC_UART_DEBUG) += uart.c
ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c
ramstage-y += cpu.c
@@ -51,11 +50,10 @@
ramstage-y += graphics.c
ramstage-y += heci.c
ramstage-y += i2c.c
-ramstage-$(CONFIG_SOC_UART_DEBUG) += uart_early.c
ramstage-y += lpc.c
ramstage-y += memmap.c
ramstage-y += mmap_boot.c
-ramstage-y += uart.c
+ramstage-$(CONFIG_SOC_UART_DEBUG) += uart.c
ramstage-y += nhlt.c
ramstage-y += spi.c
ramstage-y += systemagent.c
@@ -69,7 +67,7 @@
postcar-y += memmap.c
postcar-y += mmap_boot.c
postcar-y += spi.c
-postcar-$(CONFIG_SOC_UART_DEBUG) += uart_early.c
+postcar-$(CONFIG_SOC_UART_DEBUG) += uart.c
postcar-$(CONFIG_FSP_CAR) += exit_car_fsp.S
@@ -78,7 +76,7 @@
verstage-y += heci.c
verstage-y += memmap.c
verstage-y += mmap_boot.c
-verstage-$(CONFIG_SOC_UART_DEBUG) += uart_early.c
+verstage-$(CONFIG_SOC_UART_DEBUG) += uart.c
verstage-y += pmutil.c
verstage-y += reset.c
verstage-y += spi.c
diff --git a/src/soc/intel/apollolake/uart.c b/src/soc/intel/apollolake/uart.c
index 673039c..54b280d 100644
--- a/src/soc/intel/apollolake/uart.c
+++ b/src/soc/intel/apollolake/uart.c
@@ -1,7 +1,7 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2015 Intel Corp.
+ * Copyright (C) 2015-2017 Intel Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -21,11 +21,60 @@
*/
#include <cbmem.h>
+#include <console/uart.h>
#include <device/device.h>
#include <device/pci.h>
#include <intelblocks/uart.h>
+#include <soc/gpio.h>
#include <soc/nvs.h>
#include <soc/pci_devs.h>
+#include <soc/uart.h>
+
+static const struct pad_config uart_gpios[] = {
+#if IS_ENABLED(CONFIG_SOC_INTEL_GLK)
+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_60, NATIVE, DEEP, NF1, HIZCRx1,
+ DISPUPD), /* LPSS_UART0_RXD */
+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_61, NATIVE, DEEP, NF1, HIZCRx1,
+ DISPUPD), /* LPSS_UART0_TXD */
+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_64, NATIVE, DEEP, NF1, HIZCRx1,
+ DISPUPD), /* LPSS_UART2_RXD */
+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_65, NATIVE, DEEP, NF1, HIZCRx1,
+ DISPUPD), /* LPSS_UART2_TXD */
+#else
+ PAD_CFG_NF(GPIO_42, NATIVE, DEEP, NF1), /* UART1 RX */
+ PAD_CFG_NF(GPIO_43, NATIVE, DEEP, NF1), /* UART1 TX */
+ PAD_CFG_NF(GPIO_46, NATIVE, DEEP, NF1), /* UART2 RX */
+ PAD_CFG_NF(GPIO_47, NATIVE, DEEP, NF1), /* UART2 TX */
+#endif
+};
+
+static inline int invalid_uart_for_console(void)
+{
+ /* There are actually only 2 UARTS, and they are named UART1 and
+ * UART2. They live at pci functions 1 and 2 respectively. */
+ if (CONFIG_UART_FOR_CONSOLE > 2 || CONFIG_UART_FOR_CONSOLE < 1)
+ return 1;
+ return 0;
+}
+
+void pch_uart_init(void)
+{
+ uintptr_t base = CONFIG_CONSOLE_UART_BASE_ADDRESS;
+ device_t uart = _PCH_DEV(UART, CONFIG_UART_FOR_CONSOLE & 3);
+
+ /* Get a 0-based pad index. See invalid_uart_for_console() above. */
+ const int pad_index = CONFIG_UART_FOR_CONSOLE - 1;
+
+ if (invalid_uart_for_console())
+ return;
+
+ /* Configure the 2 pads per UART. */
+ gpio_configure_pads(&uart_gpios[pad_index * 2], 2);
+
+ /* Program UART2 BAR0, command, reset and clock register */
+ uart_common_init(uart, base);
+
+}
#if !ENV_SMM
void pch_uart_read_resources(struct device *dev)
@@ -55,3 +104,8 @@
{
return _PCH_DEV(UART, CONFIG_UART_FOR_CONSOLE);
}
+
+uintptr_t uart_platform_base(int idx)
+{
+ return CONFIG_CONSOLE_UART_BASE_ADDRESS;
+}
diff --git a/src/soc/intel/apollolake/uart_early.c b/src/soc/intel/apollolake/uart_early.c
deleted file mode 100644
index d3c1b0d..0000000
--- a/src/soc/intel/apollolake/uart_early.c
+++ /dev/null
@@ -1,74 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2015 Intel Corp.
- * (Written by Alexandru Gagniuc <alexandrux.gagniuc at intel.com> for Intel Corp.)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <console/uart.h>
-#include <device/pci.h>
-#include <intelblocks/uart.h>
-#include <soc/gpio.h>
-#include <soc/uart.h>
-#include <soc/pci_devs.h>
-
-static inline int invalid_uart_for_console(void)
-{
- /* There are actually only 2 UARTS, and they are named UART1 and
- * UART2. They live at pci functions 1 and 2 respectively. */
- if (CONFIG_UART_FOR_CONSOLE > 2 || CONFIG_UART_FOR_CONSOLE < 1)
- return 1;
- return 0;
-}
-
-uintptr_t uart_platform_base(int idx)
-{
- return CONFIG_CONSOLE_UART_BASE_ADDRESS;
-}
-
-static const struct pad_config uart_gpios[] = {
-#if IS_ENABLED(CONFIG_SOC_INTEL_GLK)
- PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_60, NATIVE, DEEP, NF1, HIZCRx1,
- DISPUPD), /* LPSS_UART0_RXD */
- PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_61, NATIVE, DEEP, NF1, HIZCRx1,
- DISPUPD), /* LPSS_UART0_TXD */
- PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_64, NATIVE, DEEP, NF1, HIZCRx1,
- DISPUPD), /* LPSS_UART2_RXD */
- PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_65, NATIVE, DEEP, NF1, HIZCRx1,
- DISPUPD), /* LPSS_UART2_TXD */
-#else
- PAD_CFG_NF(GPIO_42, NATIVE, DEEP, NF1), /* UART1 RX */
- PAD_CFG_NF(GPIO_43, NATIVE, DEEP, NF1), /* UART1 TX */
- PAD_CFG_NF(GPIO_46, NATIVE, DEEP, NF1), /* UART2 RX */
- PAD_CFG_NF(GPIO_47, NATIVE, DEEP, NF1), /* UART2 TX */
-#endif
-};
-
-void pch_uart_init(void)
-{
- uintptr_t base = CONFIG_CONSOLE_UART_BASE_ADDRESS;
- device_t uart = _PCH_DEV(UART, CONFIG_UART_FOR_CONSOLE & 3);
-
- /* Get a 0-based pad index. See invalid_uart_for_console() above. */
- const int pad_index = CONFIG_UART_FOR_CONSOLE - 1;
-
- if (invalid_uart_for_console())
- return;
-
- /* Configure the 2 pads per UART. */
- gpio_configure_pads(&uart_gpios[pad_index * 2], 2);
-
- /* Program UART2 BAR0, command, reset and clock register */
- uart_common_init(uart, base);
-
-}
--
To view, visit https://review.coreboot.org/22754
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I9a30258ba43ee5920f585c1bd06bc25773778ec4
Gerrit-Change-Number: 22754
Gerrit-PatchSet: 1
Gerrit-Owner: Aamir Bohra <aamir.bohra at intel.com>
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