<p>Aamir Bohra has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/22754">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/intel/apollolake: Clean up UART code<br><br>Clean up and move UART related code under a single uart.c file.<br><br>Change-Id: I9a30258ba43ee5920f585c1bd06bc25773778ec4<br>Signed-off-by: Aamir Bohra <aamir.bohra@intel.com><br>---<br>M src/soc/intel/apollolake/Makefile.inc<br>M src/soc/intel/apollolake/uart.c<br>D src/soc/intel/apollolake/uart_early.c<br>3 files changed, 61 insertions(+), 83 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/22754/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc<br>index 60f4ee3..68f2947 100644<br>--- a/src/soc/intel/apollolake/Makefile.inc<br>+++ b/src/soc/intel/apollolake/Makefile.inc<br>@@ -16,14 +16,14 @@<br> bootblock-y += mmap_boot.c<br> bootblock-y += pmutil.c<br> bootblock-y += spi.c<br>-bootblock-$(CONFIG_SOC_UART_DEBUG) += uart_early.c<br>+bootblock-$(CONFIG_SOC_UART_DEBUG) += uart.c<br> bootblock-$(CONFIG_FSP_CAR) += bootblock/cache_as_ram_fsp.S<br> <br> romstage-y += car.c<br> romstage-$(CONFIG_PLATFORM_USES_FSP2_0) += romstage.c<br> romstage-y += heci.c<br> romstage-y += i2c.c<br>-romstage-$(CONFIG_SOC_UART_DEBUG) += uart_early.c<br>+romstage-$(CONFIG_SOC_UART_DEBUG) += uart.c<br> romstage-y += memmap.c<br> romstage-y += meminit.c<br> ifeq ($(CONFIG_SOC_INTEL_GLK),y)<br>@@ -40,8 +40,7 @@<br> smm-y += pmutil.c<br> smm-y += smihandler.c<br> smm-y += spi.c<br>-smm-y += uart_early.c<br>-smm-y += uart.c<br>+smm-$(CONFIG_SOC_UART_DEBUG) += uart.c<br> <br> ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c<br> ramstage-y += cpu.c<br>@@ -51,11 +50,10 @@<br> ramstage-y += graphics.c<br> ramstage-y += heci.c<br> ramstage-y += i2c.c<br>-ramstage-$(CONFIG_SOC_UART_DEBUG) += uart_early.c<br> ramstage-y += lpc.c<br> ramstage-y += memmap.c<br> ramstage-y += mmap_boot.c<br>-ramstage-y += uart.c<br>+ramstage-$(CONFIG_SOC_UART_DEBUG) += uart.c<br> ramstage-y += nhlt.c<br> ramstage-y += spi.c<br> ramstage-y += systemagent.c<br>@@ -69,7 +67,7 @@<br> postcar-y += memmap.c<br> postcar-y += mmap_boot.c<br> postcar-y += spi.c<br>-postcar-$(CONFIG_SOC_UART_DEBUG) += uart_early.c<br>+postcar-$(CONFIG_SOC_UART_DEBUG) += uart.c<br> <br> postcar-$(CONFIG_FSP_CAR) += exit_car_fsp.S<br> <br>@@ -78,7 +76,7 @@<br> verstage-y += heci.c<br> verstage-y += memmap.c<br> verstage-y += mmap_boot.c<br>-verstage-$(CONFIG_SOC_UART_DEBUG) += uart_early.c<br>+verstage-$(CONFIG_SOC_UART_DEBUG) += uart.c<br> verstage-y += pmutil.c<br> verstage-y += reset.c<br> verstage-y += spi.c<br>diff --git a/src/soc/intel/apollolake/uart.c b/src/soc/intel/apollolake/uart.c<br>index 673039c..54b280d 100644<br>--- a/src/soc/intel/apollolake/uart.c<br>+++ b/src/soc/intel/apollolake/uart.c<br>@@ -1,7 +1,7 @@<br> /*<br> * This file is part of the coreboot project.<br> *<br>- * Copyright (C) 2015 Intel Corp.<br>+ * Copyright (C) 2015-2017 Intel Corp.<br> *<br> * This program is free software; you can redistribute it and/or modify<br> * it under the terms of the GNU General Public License as published by<br>@@ -21,11 +21,60 @@<br> */<br> <br> #include <cbmem.h><br>+#include <console/uart.h><br> #include <device/device.h><br> #include <device/pci.h><br> #include <intelblocks/uart.h><br>+#include <soc/gpio.h><br> #include <soc/nvs.h><br> #include <soc/pci_devs.h><br>+#include <soc/uart.h><br>+<br>+static const struct pad_config uart_gpios[] = {<br>+#if IS_ENABLED(CONFIG_SOC_INTEL_GLK)<br>+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_60, NATIVE, DEEP, NF1, HIZCRx1,<br>+ DISPUPD), /* LPSS_UART0_RXD */<br>+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_61, NATIVE, DEEP, NF1, HIZCRx1,<br>+ DISPUPD), /* LPSS_UART0_TXD */<br>+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_64, NATIVE, DEEP, NF1, HIZCRx1,<br>+ DISPUPD), /* LPSS_UART2_RXD */<br>+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_65, NATIVE, DEEP, NF1, HIZCRx1,<br>+ DISPUPD), /* LPSS_UART2_TXD */<br>+#else<br>+ PAD_CFG_NF(GPIO_42, NATIVE, DEEP, NF1), /* UART1 RX */<br>+ PAD_CFG_NF(GPIO_43, NATIVE, DEEP, NF1), /* UART1 TX */<br>+ PAD_CFG_NF(GPIO_46, NATIVE, DEEP, NF1), /* UART2 RX */<br>+ PAD_CFG_NF(GPIO_47, NATIVE, DEEP, NF1), /* UART2 TX */<br>+#endif<br>+};<br>+<br>+static inline int invalid_uart_for_console(void)<br>+{<br>+ /* There are actually only 2 UARTS, and they are named UART1 and<br>+ * UART2. They live at pci functions 1 and 2 respectively. */<br>+ if (CONFIG_UART_FOR_CONSOLE > 2 || CONFIG_UART_FOR_CONSOLE < 1)<br>+ return 1;<br>+ return 0;<br>+}<br>+<br>+void pch_uart_init(void)<br>+{<br>+ uintptr_t base = CONFIG_CONSOLE_UART_BASE_ADDRESS;<br>+ device_t uart = _PCH_DEV(UART, CONFIG_UART_FOR_CONSOLE & 3);<br>+<br>+ /* Get a 0-based pad index. See invalid_uart_for_console() above. */<br>+ const int pad_index = CONFIG_UART_FOR_CONSOLE - 1;<br>+<br>+ if (invalid_uart_for_console())<br>+ return;<br>+<br>+ /* Configure the 2 pads per UART. */<br>+ gpio_configure_pads(&uart_gpios[pad_index * 2], 2);<br>+<br>+ /* Program UART2 BAR0, command, reset and clock register */<br>+ uart_common_init(uart, base);<br>+<br>+}<br> <br> #if !ENV_SMM<br> void pch_uart_read_resources(struct device *dev)<br>@@ -55,3 +104,8 @@<br> {<br> return _PCH_DEV(UART, CONFIG_UART_FOR_CONSOLE);<br> }<br>+<br>+uintptr_t uart_platform_base(int idx)<br>+{<br>+ return CONFIG_CONSOLE_UART_BASE_ADDRESS;<br>+}<br>diff --git a/src/soc/intel/apollolake/uart_early.c b/src/soc/intel/apollolake/uart_early.c<br>deleted file mode 100644<br>index d3c1b0d..0000000<br>--- a/src/soc/intel/apollolake/uart_early.c<br>+++ /dev/null<br>@@ -1,74 +0,0 @@<br>-/*<br>- * This file is part of the coreboot project.<br>- *<br>- * Copyright (C) 2015 Intel Corp.<br>- * (Written by Alexandru Gagniuc <alexandrux.gagniuc@intel.com> for Intel Corp.)<br>- *<br>- * This program is free software; you can redistribute it and/or modify<br>- * it under the terms of the GNU General Public License as published by<br>- * the Free Software Foundation; either version 2 of the License, or<br>- * (at your option) any later version.<br>- *<br>- * This program is distributed in the hope that it will be useful,<br>- * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>- * GNU General Public License for more details.<br>- */<br>-<br>-#include <console/uart.h><br>-#include <device/pci.h><br>-#include <intelblocks/uart.h><br>-#include <soc/gpio.h><br>-#include <soc/uart.h><br>-#include <soc/pci_devs.h><br>-<br>-static inline int invalid_uart_for_console(void)<br>-{<br>- /* There are actually only 2 UARTS, and they are named UART1 and<br>- * UART2. They live at pci functions 1 and 2 respectively. */<br>- if (CONFIG_UART_FOR_CONSOLE > 2 || CONFIG_UART_FOR_CONSOLE < 1)<br>- return 1;<br>- return 0;<br>-}<br>-<br>-uintptr_t uart_platform_base(int idx)<br>-{<br>- return CONFIG_CONSOLE_UART_BASE_ADDRESS;<br>-}<br>-<br>-static const struct pad_config uart_gpios[] = {<br>-#if IS_ENABLED(CONFIG_SOC_INTEL_GLK)<br>- PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_60, NATIVE, DEEP, NF1, HIZCRx1,<br>- DISPUPD), /* LPSS_UART0_RXD */<br>- PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_61, NATIVE, DEEP, NF1, HIZCRx1,<br>- DISPUPD), /* LPSS_UART0_TXD */<br>- PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_64, NATIVE, DEEP, NF1, HIZCRx1,<br>- DISPUPD), /* LPSS_UART2_RXD */<br>- PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_65, NATIVE, DEEP, NF1, HIZCRx1,<br>- DISPUPD), /* LPSS_UART2_TXD */<br>-#else<br>- PAD_CFG_NF(GPIO_42, NATIVE, DEEP, NF1), /* UART1 RX */<br>- PAD_CFG_NF(GPIO_43, NATIVE, DEEP, NF1), /* UART1 TX */<br>- PAD_CFG_NF(GPIO_46, NATIVE, DEEP, NF1), /* UART2 RX */<br>- PAD_CFG_NF(GPIO_47, NATIVE, DEEP, NF1), /* UART2 TX */<br>-#endif<br>-};<br>-<br>-void pch_uart_init(void)<br>-{<br>- uintptr_t base = CONFIG_CONSOLE_UART_BASE_ADDRESS;<br>- device_t uart = _PCH_DEV(UART, CONFIG_UART_FOR_CONSOLE & 3);<br>-<br>- /* Get a 0-based pad index. See invalid_uart_for_console() above. */<br>- const int pad_index = CONFIG_UART_FOR_CONSOLE - 1;<br>-<br>- if (invalid_uart_for_console())<br>- return;<br>-<br>- /* Configure the 2 pads per UART. */<br>- gpio_configure_pads(&uart_gpios[pad_index * 2], 2);<br>-<br>- /* Program UART2 BAR0, command, reset and clock register */<br>- uart_common_init(uart, base);<br>-<br>-}<br></pre><p>To view, visit <a href="https://review.coreboot.org/22754">change 22754</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/22754"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I9a30258ba43ee5920f585c1bd06bc25773778ec4 </div>
<div style="display:none"> Gerrit-Change-Number: 22754 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Aamir Bohra <aamir.bohra@intel.com> </div>