[coreboot-gerrit] Change in coreboot[master]: amd/stoneyridge: Add S3 support to POST
Marshall Dawson (Code Review)
gerrit at coreboot.org
Tue Dec 5 18:08:57 CET 2017
Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/22731
Change subject: amd/stoneyridge: Add S3 support to POST
......................................................................
amd/stoneyridge: Add S3 support to POST
Add/update the romstage and ramstage paths to check for S3 resume
and call the appropriate AGESA functions. Add a call to mtrr_restore
during each core's initialization.
Change-Id: Ie6ae66f88b888fff3a800b4ed55dd1f6fed712b2
Signed-off-by: Marshall Dawson <marshalldawson3rd at gmail.com>
---
M src/soc/amd/stoneyridge/chip.c
M src/soc/amd/stoneyridge/model_15_init.c
M src/soc/amd/stoneyridge/northbridge.c
M src/soc/amd/stoneyridge/romstage.c
4 files changed, 65 insertions(+), 36 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/22731/1
diff --git a/src/soc/amd/stoneyridge/chip.c b/src/soc/amd/stoneyridge/chip.c
index 8e4ab2e..06d50c0 100644
--- a/src/soc/amd/stoneyridge/chip.c
+++ b/src/soc/amd/stoneyridge/chip.c
@@ -20,6 +20,7 @@
#include <cpu/cpu.h>
#include <device/device.h>
#include <device/pci.h>
+#include <romstage_handoff.h>
#include <soc/cpu.h>
#include <soc/northbridge.h>
#include <soc/southbridge.h>
@@ -81,12 +82,20 @@
static void earliest_ramstage(void *unused)
{
- post_code(0x46);
- if (IS_ENABLED(CONFIG_SOC_AMD_PSP_SELECTABLE_SMU_FW))
- psp_load_named_blob(MBOX_BIOS_CMD_SMU_FW2, "smu_fw2");
+ if (!romstage_handoff_is_resume()) {
+ post_code(0x46);
+ if (IS_ENABLED(CONFIG_SOC_AMD_PSP_SELECTABLE_SMU_FW))
+ psp_load_named_blob(MBOX_BIOS_CMD_SMU_FW2, "smu_fw2");
- post_code(0x47);
- AGESAWRAPPER(amdinitenv);
+ post_code(0x47);
+ AGESAWRAPPER(amdinitenv);
+ } else {
+ post_code(0x46);
+ AGESAWRAPPER(amds3laterestore);
+
+ post_code(0x47);
+ AGESAWRAPPER(fchs3earlyrestore);
+ }
}
BOOT_STATE_INIT_ENTRY(BS_PRE_DEVICE, BS_ON_ENTRY, earliest_ramstage, NULL);
diff --git a/src/soc/amd/stoneyridge/model_15_init.c b/src/soc/amd/stoneyridge/model_15_init.c
index 930e395..d420e22 100644
--- a/src/soc/amd/stoneyridge/model_15_init.c
+++ b/src/soc/amd/stoneyridge/model_15_init.c
@@ -22,12 +22,13 @@
#include <cpu/x86/msr.h>
#include <cpu/x86/pae.h>
#include <pc80/mc146818rtc.h>
-
#include <cpu/cpu.h>
#include <cpu/x86/cache.h>
#include <cpu/x86/mtrr.h>
#include <cpu/amd/amdfam15.h>
+#include <romstage_handoff.h>
#include <arch/acpi.h>
+#include <s3_resume.h>
static void msr_rw_dram(unsigned int reg)
{
@@ -69,6 +70,9 @@
msr.lo |= SYSCFG_MSR_MtrrFixDramEn;
wrmsr(SYSCFG_MSR, msr);
+ if (acpi_s3_resume_allowed() && romstage_handoff_is_resume())
+ restore_mtrr();
+
x86_enable_cache();
/* zero the machine check error status registers */
diff --git a/src/soc/amd/stoneyridge/northbridge.c b/src/soc/amd/stoneyridge/northbridge.c
index 3eb8e8d..304030b 100644
--- a/src/soc/amd/stoneyridge/northbridge.c
+++ b/src/soc/amd/stoneyridge/northbridge.c
@@ -28,6 +28,7 @@
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ids.h>
+#include <romstage_handoff.h>
#include <agesawrapper.h>
#include <agesawrapper_call.h>
#include <soc/northbridge.h>
@@ -423,12 +424,11 @@
void domain_enable_resources(device_t dev)
{
- if (acpi_is_wakeup_s3())
- AGESAWRAPPER(fchs3laterestore);
-
/* Must be called after PCI enumeration and resource allocation */
- if (!acpi_is_wakeup_s3())
+ if (!romstage_handoff_is_resume())
AGESAWRAPPER(amdinitmid);
+ else
+ AGESAWRAPPER(fchs3laterestore);
printk(BIOS_DEBUG, " ader - leaving domain_enable_resources.\n");
}
diff --git a/src/soc/amd/stoneyridge/romstage.c b/src/soc/amd/stoneyridge/romstage.c
index 32dee5a..25cbc39 100644
--- a/src/soc/amd/stoneyridge/romstage.c
+++ b/src/soc/amd/stoneyridge/romstage.c
@@ -15,6 +15,7 @@
*/
#include <arch/cpu.h>
+#include <arch/acpi.h>
#include <cpu/x86/msr.h>
#include <cpu/x86/mtrr.h>
#include <cpu/amd/mtrr.h>
@@ -24,6 +25,7 @@
#include <device/device.h>
#include <chip.h>
#include <program_loading.h>
+#include <romstage_handoff.h>
#include <agesawrapper.h>
#include <agesawrapper_call.h>
#include <soc/northbridge.h>
@@ -40,45 +42,59 @@
msr_t base, mask;
msr_t mtrr_cap = rdmsr(MTRR_CAP_MSR);
int vmtrrs = mtrr_cap.lo & MTRR_CAP_VCNT;
+ int s3_resume = acpi_s3_resume_allowed() && acpi_is_wakeup_s3();
+;
int i;
console_init();
- post_code(0x40);
- AGESAWRAPPER(amdinitpost);
+ if (!s3_resume) {
+ post_code(0x40);
+ AGESAWRAPPER(amdinitpost);
- post_code(0x41);
- /*
- * TODO: This is a hack to work around current AGESA behavior. AGESA
- * needs to change to reflect that coreboot owns the MTRRs.
- *
- * After setting up DRAM, AGESA also completes the configuration of the
- * MTRRs, setting regions to WB. Anything written to memory between
- * now and and when CAR is dismantled will be in cache and lost. For
- * now, set the regions UC to ensure the writes get to DRAM.
- */
- for (i = 0 ; i < vmtrrs ; i++) {
- base = rdmsr(MTRR_PHYS_BASE(i));
- mask = rdmsr(MTRR_PHYS_MASK(i));
- if (!(mask.lo & MTRR_PHYS_MASK_VALID))
- continue;
+ post_code(0x41);
+ /*
+ * TODO: This is a hack to work around current AGESA behavior.
+ * AGESA needs to change to reflect that coreboot owns
+ * the MTRRs.
+ *
+ * After setting up DRAM, AGESA also completes the configuration
+ * of the MTRRs, setting regions to WB. Anything written to
+ * memory between now and and when CAR is dismantled will be
+ * in cache and lost. For now, set the regions UC to ensure
+ * the writes get to DRAM.
+ */
+ for (i = 0 ; i < vmtrrs ; i++) {
+ base = rdmsr(MTRR_PHYS_BASE(i));
+ mask = rdmsr(MTRR_PHYS_MASK(i));
+ if (!(mask.lo & MTRR_PHYS_MASK_VALID))
+ continue;
- if ((base.lo & 0x7) == MTRR_TYPE_WRBACK) {
- base.lo &= ~0x7;
- base.lo |= MTRR_TYPE_UNCACHEABLE;
- wrmsr(MTRR_PHYS_BASE(i), base);
+ if ((base.lo & 0x7) == MTRR_TYPE_WRBACK) {
+ base.lo &= ~0x7;
+ base.lo |= MTRR_TYPE_UNCACHEABLE;
+ wrmsr(MTRR_PHYS_BASE(i), base);
+ }
}
+ /* Disable WB from to region 4GB-TOM2. */
+ msr_t sys_cfg = rdmsr(SYSCFG_MSR);
+ sys_cfg.lo &= ~SYSCFG_MSR_TOM2WB;
+ wrmsr(SYSCFG_MSR, sys_cfg);
+ } else {
+ printk(BIOS_INFO, "S3 detected\n");
+ post_code(0x60);
+ AGESAWRAPPER(amdinitresume);
+ restore_top_of_low_cacheable();
+
+ post_code(0x61);
}
- /* Disable WB from to region 4GB-TOM2. */
- msr_t sys_cfg = rdmsr(SYSCFG_MSR);
- sys_cfg.lo &= ~SYSCFG_MSR_TOM2WB;
- wrmsr(SYSCFG_MSR, sys_cfg);
post_code(0x42);
psp_notify_dram();
post_code(0x43);
- cbmem_initialize_empty();
+ cbmem_recovery(s3_resume);
+ romstage_handoff_init(s3_resume);
post_code(0x44);
if (postcar_frame_init(&pcf, 1 * KiB))
--
To view, visit https://review.coreboot.org/22731
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Ie6ae66f88b888fff3a800b4ed55dd1f6fed712b2
Gerrit-Change-Number: 22731
Gerrit-PatchSet: 1
Gerrit-Owner: Marshall Dawson <marshalldawson3rd at gmail.com>
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