<p>Marshall Dawson has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/22731">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">amd/stoneyridge: Add S3 support to POST<br><br>Add/update the romstage and ramstage paths to check for S3 resume<br>and call the appropriate AGESA functions. Add a call to mtrr_restore<br>during each core's initialization.<br><br>Change-Id: Ie6ae66f88b888fff3a800b4ed55dd1f6fed712b2<br>Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com><br>---<br>M src/soc/amd/stoneyridge/chip.c<br>M src/soc/amd/stoneyridge/model_15_init.c<br>M src/soc/amd/stoneyridge/northbridge.c<br>M src/soc/amd/stoneyridge/romstage.c<br>4 files changed, 65 insertions(+), 36 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/22731/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/soc/amd/stoneyridge/chip.c b/src/soc/amd/stoneyridge/chip.c<br>index 8e4ab2e..06d50c0 100644<br>--- a/src/soc/amd/stoneyridge/chip.c<br>+++ b/src/soc/amd/stoneyridge/chip.c<br>@@ -20,6 +20,7 @@<br> #include <cpu/cpu.h><br> #include <device/device.h><br> #include <device/pci.h><br>+#include <romstage_handoff.h><br> #include <soc/cpu.h><br> #include <soc/northbridge.h><br> #include <soc/southbridge.h><br>@@ -81,12 +82,20 @@<br> <br> static void earliest_ramstage(void *unused)<br> {<br>- post_code(0x46);<br>- if (IS_ENABLED(CONFIG_SOC_AMD_PSP_SELECTABLE_SMU_FW))<br>- psp_load_named_blob(MBOX_BIOS_CMD_SMU_FW2, "smu_fw2");<br>+ if (!romstage_handoff_is_resume()) {<br>+ post_code(0x46);<br>+ if (IS_ENABLED(CONFIG_SOC_AMD_PSP_SELECTABLE_SMU_FW))<br>+ psp_load_named_blob(MBOX_BIOS_CMD_SMU_FW2, "smu_fw2");<br> <br>- post_code(0x47);<br>- AGESAWRAPPER(amdinitenv);<br>+ post_code(0x47);<br>+ AGESAWRAPPER(amdinitenv);<br>+ } else {<br>+ post_code(0x46);<br>+ AGESAWRAPPER(amds3laterestore);<br>+<br>+ post_code(0x47);<br>+ AGESAWRAPPER(fchs3earlyrestore);<br>+ }<br> }<br> <br> BOOT_STATE_INIT_ENTRY(BS_PRE_DEVICE, BS_ON_ENTRY, earliest_ramstage, NULL);<br>diff --git a/src/soc/amd/stoneyridge/model_15_init.c b/src/soc/amd/stoneyridge/model_15_init.c<br>index 930e395..d420e22 100644<br>--- a/src/soc/amd/stoneyridge/model_15_init.c<br>+++ b/src/soc/amd/stoneyridge/model_15_init.c<br>@@ -22,12 +22,13 @@<br> #include <cpu/x86/msr.h><br> #include <cpu/x86/pae.h><br> #include <pc80/mc146818rtc.h><br>-<br> #include <cpu/cpu.h><br> #include <cpu/x86/cache.h><br> #include <cpu/x86/mtrr.h><br> #include <cpu/amd/amdfam15.h><br>+#include <romstage_handoff.h><br> #include <arch/acpi.h><br>+#include <s3_resume.h><br> <br> static void msr_rw_dram(unsigned int reg)<br> {<br>@@ -69,6 +70,9 @@<br> msr.lo |= SYSCFG_MSR_MtrrFixDramEn;<br> wrmsr(SYSCFG_MSR, msr);<br> <br>+ if (acpi_s3_resume_allowed() && romstage_handoff_is_resume())<br>+ restore_mtrr();<br>+<br> x86_enable_cache();<br> <br> /* zero the machine check error status registers */<br>diff --git a/src/soc/amd/stoneyridge/northbridge.c b/src/soc/amd/stoneyridge/northbridge.c<br>index 3eb8e8d..304030b 100644<br>--- a/src/soc/amd/stoneyridge/northbridge.c<br>+++ b/src/soc/amd/stoneyridge/northbridge.c<br>@@ -28,6 +28,7 @@<br> #include <device/device.h><br> #include <device/pci.h><br> #include <device/pci_ids.h><br>+#include <romstage_handoff.h><br> #include <agesawrapper.h><br> #include <agesawrapper_call.h><br> #include <soc/northbridge.h><br>@@ -423,12 +424,11 @@<br> <br> void domain_enable_resources(device_t dev)<br> {<br>- if (acpi_is_wakeup_s3())<br>- AGESAWRAPPER(fchs3laterestore);<br>-<br> /* Must be called after PCI enumeration and resource allocation */<br>- if (!acpi_is_wakeup_s3())<br>+ if (!romstage_handoff_is_resume())<br> AGESAWRAPPER(amdinitmid);<br>+ else<br>+ AGESAWRAPPER(fchs3laterestore);<br> <br> printk(BIOS_DEBUG, " ader - leaving domain_enable_resources.\n");<br> }<br>diff --git a/src/soc/amd/stoneyridge/romstage.c b/src/soc/amd/stoneyridge/romstage.c<br>index 32dee5a..25cbc39 100644<br>--- a/src/soc/amd/stoneyridge/romstage.c<br>+++ b/src/soc/amd/stoneyridge/romstage.c<br>@@ -15,6 +15,7 @@<br> */<br> <br> #include <arch/cpu.h><br>+#include <arch/acpi.h><br> #include <cpu/x86/msr.h><br> #include <cpu/x86/mtrr.h><br> #include <cpu/amd/mtrr.h><br>@@ -24,6 +25,7 @@<br> #include <device/device.h><br> #include <chip.h><br> #include <program_loading.h><br>+#include <romstage_handoff.h><br> #include <agesawrapper.h><br> #include <agesawrapper_call.h><br> #include <soc/northbridge.h><br>@@ -40,45 +42,59 @@<br> msr_t base, mask;<br> msr_t mtrr_cap = rdmsr(MTRR_CAP_MSR);<br> int vmtrrs = mtrr_cap.lo & MTRR_CAP_VCNT;<br>+ int s3_resume = acpi_s3_resume_allowed() && acpi_is_wakeup_s3();<br>+;<br> int i;<br> <br> console_init();<br> <br>- post_code(0x40);<br>- AGESAWRAPPER(amdinitpost);<br>+ if (!s3_resume) {<br>+ post_code(0x40);<br>+ AGESAWRAPPER(amdinitpost);<br> <br>- post_code(0x41);<br>- /*<br>- * TODO: This is a hack to work around current AGESA behavior. AGESA<br>- * needs to change to reflect that coreboot owns the MTRRs.<br>- *<br>- * After setting up DRAM, AGESA also completes the configuration of the<br>- * MTRRs, setting regions to WB. Anything written to memory between<br>- * now and and when CAR is dismantled will be in cache and lost. For<br>- * now, set the regions UC to ensure the writes get to DRAM.<br>- */<br>- for (i = 0 ; i < vmtrrs ; i++) {<br>- base = rdmsr(MTRR_PHYS_BASE(i));<br>- mask = rdmsr(MTRR_PHYS_MASK(i));<br>- if (!(mask.lo & MTRR_PHYS_MASK_VALID))<br>- continue;<br>+ post_code(0x41);<br>+ /*<br>+ * TODO: This is a hack to work around current AGESA behavior.<br>+ * AGESA needs to change to reflect that coreboot owns<br>+ * the MTRRs.<br>+ *<br>+ * After setting up DRAM, AGESA also completes the configuration<br>+ * of the MTRRs, setting regions to WB. Anything written to<br>+ * memory between now and and when CAR is dismantled will be<br>+ * in cache and lost. For now, set the regions UC to ensure<br>+ * the writes get to DRAM.<br>+ */<br>+ for (i = 0 ; i < vmtrrs ; i++) {<br>+ base = rdmsr(MTRR_PHYS_BASE(i));<br>+ mask = rdmsr(MTRR_PHYS_MASK(i));<br>+ if (!(mask.lo & MTRR_PHYS_MASK_VALID))<br>+ continue;<br> <br>- if ((base.lo & 0x7) == MTRR_TYPE_WRBACK) {<br>- base.lo &= ~0x7;<br>- base.lo |= MTRR_TYPE_UNCACHEABLE;<br>- wrmsr(MTRR_PHYS_BASE(i), base);<br>+ if ((base.lo & 0x7) == MTRR_TYPE_WRBACK) {<br>+ base.lo &= ~0x7;<br>+ base.lo |= MTRR_TYPE_UNCACHEABLE;<br>+ wrmsr(MTRR_PHYS_BASE(i), base);<br>+ }<br> }<br>+ /* Disable WB from to region 4GB-TOM2. */<br>+ msr_t sys_cfg = rdmsr(SYSCFG_MSR);<br>+ sys_cfg.lo &= ~SYSCFG_MSR_TOM2WB;<br>+ wrmsr(SYSCFG_MSR, sys_cfg);<br>+ } else {<br>+ printk(BIOS_INFO, "S3 detected\n");<br>+ post_code(0x60);<br>+ AGESAWRAPPER(amdinitresume);<br>+ restore_top_of_low_cacheable();<br>+<br>+ post_code(0x61);<br> }<br>- /* Disable WB from to region 4GB-TOM2. */<br>- msr_t sys_cfg = rdmsr(SYSCFG_MSR);<br>- sys_cfg.lo &= ~SYSCFG_MSR_TOM2WB;<br>- wrmsr(SYSCFG_MSR, sys_cfg);<br> <br> post_code(0x42);<br> psp_notify_dram();<br> <br> post_code(0x43);<br>- cbmem_initialize_empty();<br>+ cbmem_recovery(s3_resume);<br>+ romstage_handoff_init(s3_resume);<br> <br> post_code(0x44);<br> if (postcar_frame_init(&pcf, 1 * KiB))<br></pre><p>To view, visit <a href="https://review.coreboot.org/22731">change 22731</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/22731"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Ie6ae66f88b888fff3a800b4ed55dd1f6fed712b2 </div>
<div style="display:none"> Gerrit-Change-Number: 22731 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Marshall Dawson <marshalldawson3rd@gmail.com> </div>