[coreboot-gerrit] Change in coreboot[master]: soc/amd/stoneyridge: Add USB OC support

[Marc Jones (Code Review)]

Marc Jones has uploaded this change for review. ( https://review.coreboot.org/22678


Change subject: soc/amd/stoneyridge: Add USB OC support
......................................................................

soc/amd/stoneyridge: Add USB OC support

Add USB overcurrent support. Adds a weak call for mainboards
that don't suport USB OC.

BUG=b:69229635

Change-Id: Ie54c7a2baa78f21cf1cd30d5ed70c8c832cf3674
Signed-off-by: Marc Jones <marcj303 at gmail.com>
---
M src/soc/amd/stoneyridge/include/soc/southbridge.h
M src/soc/amd/stoneyridge/usb.c
2 files changed, 65 insertions(+), 1 deletion(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/22678/1

diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h
index f840fd9..44e6f4c 100644
--- a/src/soc/amd/stoneyridge/include/soc/southbridge.h
+++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h
@@ -268,6 +268,28 @@
 #define PWR_RESET_CFG			0x10
 #define   TOGGLE_ALL_PWR_GOOD		BIT(1)
 
+#define XHCI_PM_INDIRECT_INDEX		0x48
+#define XHCI_PM_INDIRECT_DATA		0x4C
+#define   XHCI_OVER_CURRENT_CONTROL	0x30
+
+#define EHCI_OVER_CURRENT_CONTROL	0x70
+
+#define USB_OC0				0
+#define USB_OC1				1
+#define USB_OC2				2
+#define USB_OC3				3
+#define USB_OC4				4
+#define USB_OC5				5
+#define USB_OC6				6
+#define USB_OC7				7
+#define USB_OC_DISABLE			0xf
+#define USB_OC_DISABLE_ALL		0xffff
+
+#define OC_PORT0_SHIFT		0
+#define OC_PORT1_SHIFT		4
+#define OC_PORT2_SHIFT		8
+#define OC_PORT3_SHIFT		12
+
 static inline int sb_sata_enable(void)
 {
 	/* True if IDE or AHCI. */
@@ -322,4 +344,13 @@
 int s3_save_nvram_early(u32 dword, int size, int  nvram_pos);
 void bootblock_fch_early_init(void);
 
+/*
+ * Call the mainboard to get the USB Over Current Map. The mainboard
+ * returns the map and 0 on Success or -1 on error or no map. There is
+ * a default weak function in usb.c if the mainboard doesn't have any
+ * over current support.
+ */
+int get_xhci_oc_map(uint16_t *usb_oc_map);
+int get_ehci_oc_map(uint16_t *usb_oc_map);
+
 #endif /* __STONEYRIDGE_H__ */
diff --git a/src/soc/amd/stoneyridge/usb.c b/src/soc/amd/stoneyridge/usb.c
index 82984b9..b61370e 100644
--- a/src/soc/amd/stoneyridge/usb.c
+++ b/src/soc/amd/stoneyridge/usb.c
@@ -20,7 +20,40 @@
 #include <device/pci_ops.h>
 #include <device/pci_ehci.h>
 #include <arch/io.h>
+#include <soc/pci_devs.h>
 #include <soc/southbridge.h>
+
+
+static void set_usb_over_current(device_t dev)
+{
+	uint16_t map = 0xFFFF;
+
+
+	if (dev->path.pci.devfn  ==  XHCI_DEVFN) {
+		if (get_xhci_oc_map(&map) == 0) {
+			xhci_pm_write32(XHCI_PM_INDIRECT_INDEX,
+						XHCI_OVER_CURRENT_CONTROL);
+			xhci_pm_write16(XHCI_PM_INDIRECT_DATA, (uint32_t)map);
+		}
+	}
+
+	if (dev->path.pci.devfn  ==  EHCI1_DEVFN) {
+		if (get_ehci_oc_map(&map) == 0)
+			pci_write_config16(dev, EHCI_OVER_CURRENT_CONTROL, map);
+	}
+}
+
+int __attribute__((weak)) get_xhci_oc_map(uint16_t *map)
+{
+	printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);
+	return -1;
+}
+
+int __attribute__((weak)) get_ehci_oc_map(uint16_t *map)
+{
+	printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);
+	return -1;
+}
 
 static struct pci_operations lops_pci = {
 	.set_subsystem = pci_dev_set_subsystem,
@@ -30,7 +63,7 @@
 	.read_resources = pci_ehci_read_resources,
 	.set_resources = pci_dev_set_resources,
 	.enable_resources = pci_dev_enable_resources,
-	.init = NULL,
+	.init = set_usb_over_current,
 	.scan_bus = NULL,
 	.ops_pci = &lops_pci,
 };

-- 
To view, visit https://review.coreboot.org/22678
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Ie54c7a2baa78f21cf1cd30d5ed70c8c832cf3674
Gerrit-Change-Number: 22678
Gerrit-PatchSet: 1
Gerrit-Owner: Marc Jones <marc at marcjonesconsulting.com>
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