<p>Marc Jones has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/22678">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/amd/stoneyridge: Add USB OC support<br><br>Add USB overcurrent support. Adds a weak call for mainboards<br>that don't suport USB OC.<br><br>BUG=b:69229635<br><br>Change-Id: Ie54c7a2baa78f21cf1cd30d5ed70c8c832cf3674<br>Signed-off-by: Marc Jones <marcj303@gmail.com><br>---<br>M src/soc/amd/stoneyridge/include/soc/southbridge.h<br>M src/soc/amd/stoneyridge/usb.c<br>2 files changed, 65 insertions(+), 1 deletion(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/22678/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h<br>index f840fd9..44e6f4c 100644<br>--- a/src/soc/amd/stoneyridge/include/soc/southbridge.h<br>+++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h<br>@@ -268,6 +268,28 @@<br> #define PWR_RESET_CFG 0x10<br> #define TOGGLE_ALL_PWR_GOOD BIT(1)<br> <br>+#define XHCI_PM_INDIRECT_INDEX 0x48<br>+#define XHCI_PM_INDIRECT_DATA 0x4C<br>+#define XHCI_OVER_CURRENT_CONTROL 0x30<br>+<br>+#define EHCI_OVER_CURRENT_CONTROL 0x70<br>+<br>+#define USB_OC0 0<br>+#define USB_OC1 1<br>+#define USB_OC2 2<br>+#define USB_OC3 3<br>+#define USB_OC4 4<br>+#define USB_OC5 5<br>+#define USB_OC6 6<br>+#define USB_OC7 7<br>+#define USB_OC_DISABLE 0xf<br>+#define USB_OC_DISABLE_ALL 0xffff<br>+<br>+#define OC_PORT0_SHIFT 0<br>+#define OC_PORT1_SHIFT 4<br>+#define OC_PORT2_SHIFT 8<br>+#define OC_PORT3_SHIFT 12<br>+<br> static inline int sb_sata_enable(void)<br> {<br> /* True if IDE or AHCI. */<br>@@ -322,4 +344,13 @@<br> int s3_save_nvram_early(u32 dword, int size, int nvram_pos);<br> void bootblock_fch_early_init(void);<br> <br>+/*<br>+ * Call the mainboard to get the USB Over Current Map. The mainboard<br>+ * returns the map and 0 on Success or -1 on error or no map. There is<br>+ * a default weak function in usb.c if the mainboard doesn't have any<br>+ * over current support.<br>+ */<br>+int get_xhci_oc_map(uint16_t *usb_oc_map);<br>+int get_ehci_oc_map(uint16_t *usb_oc_map);<br>+<br> #endif /* __STONEYRIDGE_H__ */<br>diff --git a/src/soc/amd/stoneyridge/usb.c b/src/soc/amd/stoneyridge/usb.c<br>index 82984b9..b61370e 100644<br>--- a/src/soc/amd/stoneyridge/usb.c<br>+++ b/src/soc/amd/stoneyridge/usb.c<br>@@ -20,7 +20,40 @@<br> #include <device/pci_ops.h><br> #include <device/pci_ehci.h><br> #include <arch/io.h><br>+#include <soc/pci_devs.h><br> #include <soc/southbridge.h><br>+<br>+<br>+static void set_usb_over_current(device_t dev)<br>+{<br>+ uint16_t map = 0xFFFF;<br>+<br>+<br>+ if (dev->path.pci.devfn == XHCI_DEVFN) {<br>+ if (get_xhci_oc_map(&map) == 0) {<br>+ xhci_pm_write32(XHCI_PM_INDIRECT_INDEX,<br>+ XHCI_OVER_CURRENT_CONTROL);<br>+ xhci_pm_write16(XHCI_PM_INDIRECT_DATA, (uint32_t)map);<br>+ }<br>+ }<br>+<br>+ if (dev->path.pci.devfn == EHCI1_DEVFN) {<br>+ if (get_ehci_oc_map(&map) == 0)<br>+ pci_write_config16(dev, EHCI_OVER_CURRENT_CONTROL, map);<br>+ }<br>+}<br>+<br>+int __attribute__((weak)) get_xhci_oc_map(uint16_t *map)<br>+{<br>+ printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);<br>+ return -1;<br>+}<br>+<br>+int __attribute__((weak)) get_ehci_oc_map(uint16_t *map)<br>+{<br>+ printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);<br>+ return -1;<br>+}<br> <br> static struct pci_operations lops_pci = {<br> .set_subsystem = pci_dev_set_subsystem,<br>@@ -30,7 +63,7 @@<br> .read_resources = pci_ehci_read_resources,<br> .set_resources = pci_dev_set_resources,<br> .enable_resources = pci_dev_enable_resources,<br>- .init = NULL,<br>+ .init = set_usb_over_current,<br> .scan_bus = NULL,<br> .ops_pci = &lops_pci,<br> };<br></pre><p>To view, visit <a href="https://review.coreboot.org/22678">change 22678</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/22678"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Ie54c7a2baa78f21cf1cd30d5ed70c8c832cf3674 </div>
<div style="display:none"> Gerrit-Change-Number: 22678 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Marc Jones <marc@marcjonesconsulting.com> </div>