[coreboot-gerrit] Change in coreboot[master]: soc/intel/apollolake: Add PrmrrSize and SGX enable config

[Pratikkumar V Prajapati (Code Review)]

Pratikkumar V Prajapati has uploaded this change for review. ( https://review.coreboot.org/21274


Change subject: soc/intel/apollolake: Add PrmrrSize and SGX enable config
......................................................................

soc/intel/apollolake: Add PrmrrSize and SGX enable config

Add PrmrrSize and sgx_enable config option. PrmrrSize gets
configured in romstage so that FSP can allocate memory for SGX.

Change-Id: I56165ca201163a8b8b522e9aeb47bd1f4267be5e
Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati at intel.com>
---
M src/soc/intel/apollolake/chip.h
M src/soc/intel/apollolake/romstage.c
2 files changed, 21 insertions(+), 0 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/21274/1

diff --git a/src/soc/intel/apollolake/chip.h b/src/soc/intel/apollolake/chip.h
index 33e2dad..750f53a 100644
--- a/src/soc/intel/apollolake/chip.h
+++ b/src/soc/intel/apollolake/chip.h
@@ -117,6 +117,15 @@
 
 	/* GPIO SD card detect pin */
 	unsigned int sdcard_cd_gpio;
+
+	/* PRMRR size setting with three options
+	 *  0x02000000 - 32MiB
+	 *  0x04000000 - 64MiB
+	 *  0x08000000 - 128MiB */
+	uint32_t PrmrrSize;
+
+	/* Enable SGX feature */
+	uint8_t sgx_enable;
 };
 
 typedef struct soc_intel_apollolake_config config_t;
diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c
index 2017d84..44e781e 100644
--- a/src/soc/intel/apollolake/romstage.c
+++ b/src/soc/intel/apollolake/romstage.c
@@ -319,13 +319,25 @@
 	}
 }
 
+static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, const config_t *config)
+{
+	m_cfg->PrmrrSize = config->PrmrrSize;
+}
+
 void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
 {
+	const struct device *dev = dev_find_slot(0, PCH_DEVFN_LPC);
+	assert(dev != NULL);
+	const config_t *config = dev->chip_info;
+	FSP_M_CONFIG *m_cfg = &mupd->FspmConfig;
 	struct region_device rdev;
 
 	check_full_retrain(mupd);
 
 	fill_console_params(mupd);
+
+	soc_memory_init_params(m_cfg, config);
+
 	mainboard_memory_init_params(mupd);
 
 	/* Do NOT let FSP do any GPIO pad configuration */

-- 
To view, visit https://review.coreboot.org/21274
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I56165ca201163a8b8b522e9aeb47bd1f4267be5e
Gerrit-Change-Number: 21274
Gerrit-PatchSet: 1
Gerrit-Owner: Pratikkumar V Prajapati <pratikkumar.v.prajapati at intel.com>
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