<p>Pratikkumar V Prajapati has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/21274">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/intel/apollolake: Add PrmrrSize and SGX enable config<br><br>Add PrmrrSize and sgx_enable config option. PrmrrSize gets<br>configured in romstage so that FSP can allocate memory for SGX.<br><br>Change-Id: I56165ca201163a8b8b522e9aeb47bd1f4267be5e<br>Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com><br>---<br>M src/soc/intel/apollolake/chip.h<br>M src/soc/intel/apollolake/romstage.c<br>2 files changed, 21 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/21274/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/soc/intel/apollolake/chip.h b/src/soc/intel/apollolake/chip.h<br>index 33e2dad..750f53a 100644<br>--- a/src/soc/intel/apollolake/chip.h<br>+++ b/src/soc/intel/apollolake/chip.h<br>@@ -117,6 +117,15 @@<br> <br> /* GPIO SD card detect pin */<br> unsigned int sdcard_cd_gpio;<br>+<br>+ /* PRMRR size setting with three options<br>+ * 0x02000000 - 32MiB<br>+ * 0x04000000 - 64MiB<br>+ * 0x08000000 - 128MiB */<br>+ uint32_t PrmrrSize;<br>+<br>+ /* Enable SGX feature */<br>+ uint8_t sgx_enable;<br> };<br> <br> typedef struct soc_intel_apollolake_config config_t;<br>diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c<br>index 2017d84..44e781e 100644<br>--- a/src/soc/intel/apollolake/romstage.c<br>+++ b/src/soc/intel/apollolake/romstage.c<br>@@ -319,13 +319,25 @@<br> }<br> }<br> <br>+static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, const config_t *config)<br>+{<br>+ m_cfg->PrmrrSize = config->PrmrrSize;<br>+}<br>+<br> void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)<br> {<br>+ const struct device *dev = dev_find_slot(0, PCH_DEVFN_LPC);<br>+ assert(dev != NULL);<br>+ const config_t *config = dev->chip_info;<br>+ FSP_M_CONFIG *m_cfg = &mupd->FspmConfig;<br> struct region_device rdev;<br> <br> check_full_retrain(mupd);<br> <br> fill_console_params(mupd);<br>+<br>+ soc_memory_init_params(m_cfg, config);<br>+<br> mainboard_memory_init_params(mupd);<br> <br> /* Do NOT let FSP do any GPIO pad configuration */<br></pre><p>To view, visit <a href="https://review.coreboot.org/21274">change 21274</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/21274"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I56165ca201163a8b8b522e9aeb47bd1f4267be5e </div>
<div style="display:none"> Gerrit-Change-Number: 21274 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com> </div>