[coreboot-gerrit] Change in coreboot[master]: mainboard/intel/cannonlake_rvp: SMBus, SAGV and Skip FSP MPInit in de...
Pratikkumar V Prajapati (Code Review)
gerrit at coreboot.org
Fri Aug 25 02:40:23 CEST 2017
Pratikkumar V Prajapati has uploaded this change for review. ( https://review.coreboot.org/21198
Change subject: mainboard/intel/cannonlake_rvp: SMBus, SAGV and Skip FSP MPInit in devicetree
......................................................................
mainboard/intel/cannonlake_rvp: SMBus, SAGV and Skip FSP MPInit in devicetree
Set SMBus, SAGV and Skip FSP MPInit configuration from devicetree.cb
Change-Id: Ic810b003bf7fb13447d5d5dcd49cfcc31785b440
Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati at intel.com>
---
M src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb
M src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb
2 files changed, 10 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/21198/1
diff --git a/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb b/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb
index e71f15b..a3c4c80 100644
--- a/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb
+++ b/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb
@@ -4,6 +4,11 @@
device lapic 0 on end
end
+ # FSP configuration
+ register "SaGv" = "3"
+ register "FspSkipMpInit" = "1"
+ register "SmbusEnable" = "1"
+
device domain 0 on
device pci 00.0 on end # Host Bridge
device pci 02.0 on end # Integrated Graphics Device
diff --git a/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb b/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb
index e71f15b..a3c4c80 100644
--- a/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb
+++ b/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb
@@ -4,6 +4,11 @@
device lapic 0 on end
end
+ # FSP configuration
+ register "SaGv" = "3"
+ register "FspSkipMpInit" = "1"
+ register "SmbusEnable" = "1"
+
device domain 0 on
device pci 00.0 on end # Host Bridge
device pci 02.0 on end # Integrated Graphics Device
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Ic810b003bf7fb13447d5d5dcd49cfcc31785b440
Gerrit-Change-Number: 21198
Gerrit-PatchSet: 1
Gerrit-Owner: Pratikkumar V Prajapati <pratikkumar.v.prajapati at intel.com>
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