<p>Pratikkumar V Prajapati has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/21198">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">mainboard/intel/cannonlake_rvp: SMBus, SAGV and Skip FSP MPInit in devicetree<br><br>Set SMBus, SAGV and Skip FSP MPInit configuration from devicetree.cb<br><br>Change-Id: Ic810b003bf7fb13447d5d5dcd49cfcc31785b440<br>Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com><br>---<br>M src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb<br>M src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb<br>2 files changed, 10 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/21198/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb b/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb<br>index e71f15b..a3c4c80 100644<br>--- a/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb<br>+++ b/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb<br>@@ -4,6 +4,11 @@<br>            device lapic 0 on end<br>         end<br> <br>+       # FSP configuration<br>+  register "SaGv" = "3"<br>+    register "FspSkipMpInit" = "1"<br>+   register "SmbusEnable" = "1"<br>+<br>   device domain 0 on<br>            device pci 00.0 on  end # Host Bridge<br>                 device pci 02.0 on  end # Integrated Graphics Device<br>diff --git a/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb b/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb<br>index e71f15b..a3c4c80 100644<br>--- a/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb<br>+++ b/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb<br>@@ -4,6 +4,11 @@<br>           device lapic 0 on end<br>         end<br> <br>+       # FSP configuration<br>+  register "SaGv" = "3"<br>+    register "FspSkipMpInit" = "1"<br>+   register "SmbusEnable" = "1"<br>+<br>   device domain 0 on<br>            device pci 00.0 on  end # Host Bridge<br>                 device pci 02.0 on  end # Integrated Graphics Device<br></pre><p>To view, visit <a href="https://review.coreboot.org/21198">change 21198</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/21198"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Ic810b003bf7fb13447d5d5dcd49cfcc31785b440 </div>
<div style="display:none"> Gerrit-Change-Number: 21198 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com> </div>