[coreboot-gerrit] Change in coreboot[master]: soc/intel/common: Add functions into common system agent library

[Subrata Banik (Code Review)]

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/21133


Change subject: soc/intel/common: Add functions into common system agent library
......................................................................

soc/intel/common: Add functions into common system agent library

This patch to add helper functions for memory layout design
based on PCI Host Bridge/DRAM registers.

BRANCH=none
BUG=b:63974384
TEST=Build and boot eve successfully.

Change-Id: I95250ef493c9844b8c46528f1f7de8a42cba88a2
Signed-off-by: Subrata Banik <subrata.banik at intel.com>
---
M src/soc/intel/common/block/include/intelblocks/systemagent.h
M src/soc/intel/common/block/systemagent/systemagent.c
M src/soc/intel/common/block/systemagent/systemagent_def.h
M src/soc/intel/common/block/systemagent/systemagent_early.c
4 files changed, 80 insertions(+), 22 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/21133/1

diff --git a/src/soc/intel/common/block/include/intelblocks/systemagent.h b/src/soc/intel/common/block/include/intelblocks/systemagent.h
index 22a2b8d..5f04e36 100644
--- a/src/soc/intel/common/block/include/intelblocks/systemagent.h
+++ b/src/soc/intel/common/block/include/intelblocks/systemagent.h
@@ -73,7 +73,14 @@
 void enable_pam_region(void);
 /* API to enable Power Aware Interrupt Routing through MCHBAR */
 void enable_power_aware_intr(void);
-
+/* API to get TOLUD base address */
+uint32_t sa_get_tolud_base(void);
+/* API to get DSM size */
+size_t sa_get_dsm_size(void);
+/* API to get GSM size */
+size_t sa_get_gsm_size(void);
+/* API to get DPR size */
+size_t sa_get_dpr_size(void);
 /*
  * SoC overrides
  *
diff --git a/src/soc/intel/common/block/systemagent/systemagent.c b/src/soc/intel/common/block/systemagent/systemagent.c
index 206f4a0..cb7af41 100644
--- a/src/soc/intel/common/block/systemagent/systemagent.c
+++ b/src/soc/intel/common/block/systemagent/systemagent.c
@@ -100,26 +100,6 @@
 }
 
 /*
- * Get DPR size incase CONFIG_SA_ENABLE_DPR is selected by SoC.
- */
-static size_t get_dpr_size(void)
-{
-	uintptr_t dpr_reg;
-	size_t size = 0;
-	/*
-	 * DMA Protected Range can be reserved below TSEG for PCODE patch
-	 * or TXT/BootGuard related data.  Rather than report a base address
-	 * the DPR register reports the TOP of the region, which is the same
-	 * as TSEG base.  The region size is reported in MiB in bits 11:4.
-	 */
-	dpr_reg = pci_read_config32(SA_DEV_ROOT, DPR);
-	if (dpr_reg & DPR_EPM)
-		size = (dpr_reg & DPR_SIZE_MASK) << 16;
-
-	return size;
-}
-
-/*
  * These are the host memory ranges that should be added:
  * - 0 -> 0xa0000: cacheable
  * - 0xc0000 -> top_of_ram : cacheable
@@ -159,7 +139,7 @@
 	int index = *resource_count;
 
 	if (IS_ENABLED(CONFIG_SA_ENABLE_DPR))
-		dpr_size = get_dpr_size();
+		dpr_size = sa_get_dpr_size();
 
 	top_of_ram = (uintptr_t)cbmem_top();
 
diff --git a/src/soc/intel/common/block/systemagent/systemagent_def.h b/src/soc/intel/common/block/systemagent/systemagent_def.h
index 29ce9ec..3243c85 100644
--- a/src/soc/intel/common/block/systemagent/systemagent_def.h
+++ b/src/soc/intel/common/block/systemagent/systemagent_def.h
@@ -19,6 +19,11 @@
 
 /* Device 0:0.0 PCI configuration space */
 
+#define GGC		0x50	/* GMCH Graphics Control */
+#define  G_GMS_OFFSET	0x8
+#define  G_GMS_MASK		0xff00
+#define  G_GGMS_OFFSET	0x6
+#define  G_GGMS_MASK	0xc0
 /* DPR register incase CONFIG_SA_ENABLE_DPR is selected by SoC */
 #define DPR		0x5c
 #define  DPR_EPM	(1 << 2)
diff --git a/src/soc/intel/common/block/systemagent/systemagent_early.c b/src/soc/intel/common/block/systemagent/systemagent_early.c
index 7cf78e7..7db907a 100644
--- a/src/soc/intel/common/block/systemagent/systemagent_early.c
+++ b/src/soc/intel/common/block/systemagent/systemagent_early.c
@@ -132,3 +132,69 @@
 	bios_reset_cpl |= 3;
 	MCHBAR8(BIOS_RESET_CPL) = bios_reset_cpl;
 }
+
+uint32_t sa_get_tolud_base(void)
+{
+	/* All regions concerned for have 1 MiB alignment. */
+	return ALIGN_DOWN(pci_read_config32(SA_DEV_ROOT, TOLUD), 1*MiB);
+}
+
+static uint16_t sa_get_gcc_reg(void)
+{
+	uint16_t ggc;
+
+	ggc = pci_read_config32(SA_DEV_ROOT, GGC);
+
+	return ggc;
+}
+
+size_t sa_get_dsm_size(void)
+{
+	uint32_t dsm_size;
+
+	dsm_size = ((sa_get_gcc_reg() & G_GMS_MASK) >> G_GMS_OFFSET) * 32*MiB;
+
+	return dsm_size;
+}
+
+size_t sa_get_gsm_size(void)
+{
+	uint32_t gsm_size;
+
+	switch ((sa_get_gcc_reg() & G_GGMS_MASK) >> G_GGMS_OFFSET) {
+	case 1:
+		gsm_size = 2*MiB;
+		break;
+	case 2:
+		gsm_size = 4*MiB;
+		break;
+	case 3:
+		gsm_size = 8*MiB;
+		break;
+	default:
+		gsm_size = 0;
+		break;
+	}
+
+	return gsm_size;
+}
+
+/*
+ * Get DPR size incase CONFIG_SA_ENABLE_DPR is selected by SoC.
+ */
+size_t sa_get_dpr_size(void)
+{
+	uintptr_t dpr_reg;
+	size_t size = 0;
+	/*
+	 * DMA Protected Range can be reserved below TSEG for PCODE patch
+	 * or TXT/BootGuard related data.  Rather than report a base address
+	 * the DPR register reports the TOP of the region, which is the same
+	 * as TSEG base.  The region size is reported in MiB in bits 11:4.
+	 */
+	dpr_reg = pci_read_config32(SA_DEV_ROOT, DPR);
+	if (dpr_reg & DPR_EPM)
+		size = (dpr_reg & DPR_SIZE_MASK) << 16;
+
+	return size;
+}

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I95250ef493c9844b8c46528f1f7de8a42cba88a2
Gerrit-Change-Number: 21133
Gerrit-PatchSet: 1
Gerrit-Owner: Subrata Banik <subrata.banik at intel.com>
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