<p>Subrata Banik has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/21133">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/intel/common: Add functions into common system agent library<br><br>This patch to add helper functions for memory layout design<br>based on PCI Host Bridge/DRAM registers.<br><br>BRANCH=none<br>BUG=b:63974384<br>TEST=Build and boot eve successfully.<br><br>Change-Id: I95250ef493c9844b8c46528f1f7de8a42cba88a2<br>Signed-off-by: Subrata Banik <subrata.banik@intel.com><br>---<br>M src/soc/intel/common/block/include/intelblocks/systemagent.h<br>M src/soc/intel/common/block/systemagent/systemagent.c<br>M src/soc/intel/common/block/systemagent/systemagent_def.h<br>M src/soc/intel/common/block/systemagent/systemagent_early.c<br>4 files changed, 80 insertions(+), 22 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/21133/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/soc/intel/common/block/include/intelblocks/systemagent.h b/src/soc/intel/common/block/include/intelblocks/systemagent.h<br>index 22a2b8d..5f04e36 100644<br>--- a/src/soc/intel/common/block/include/intelblocks/systemagent.h<br>+++ b/src/soc/intel/common/block/include/intelblocks/systemagent.h<br>@@ -73,7 +73,14 @@<br> void enable_pam_region(void);<br> /* API to enable Power Aware Interrupt Routing through MCHBAR */<br> void enable_power_aware_intr(void);<br>-<br>+/* API to get TOLUD base address */<br>+uint32_t sa_get_tolud_base(void);<br>+/* API to get DSM size */<br>+size_t sa_get_dsm_size(void);<br>+/* API to get GSM size */<br>+size_t sa_get_gsm_size(void);<br>+/* API to get DPR size */<br>+size_t sa_get_dpr_size(void);<br> /*<br> * SoC overrides<br> *<br>diff --git a/src/soc/intel/common/block/systemagent/systemagent.c b/src/soc/intel/common/block/systemagent/systemagent.c<br>index 206f4a0..cb7af41 100644<br>--- a/src/soc/intel/common/block/systemagent/systemagent.c<br>+++ b/src/soc/intel/common/block/systemagent/systemagent.c<br>@@ -100,26 +100,6 @@<br> }<br> <br> /*<br>- * Get DPR size incase CONFIG_SA_ENABLE_DPR is selected by SoC.<br>- */<br>-static size_t get_dpr_size(void)<br>-{<br>- uintptr_t dpr_reg;<br>- size_t size = 0;<br>- /*<br>- * DMA Protected Range can be reserved below TSEG for PCODE patch<br>- * or TXT/BootGuard related data. Rather than report a base address<br>- * the DPR register reports the TOP of the region, which is the same<br>- * as TSEG base. The region size is reported in MiB in bits 11:4.<br>- */<br>- dpr_reg = pci_read_config32(SA_DEV_ROOT, DPR);<br>- if (dpr_reg & DPR_EPM)<br>- size = (dpr_reg & DPR_SIZE_MASK) << 16;<br>-<br>- return size;<br>-}<br>-<br>-/*<br> * These are the host memory ranges that should be added:<br> * - 0 -> 0xa0000: cacheable<br> * - 0xc0000 -> top_of_ram : cacheable<br>@@ -159,7 +139,7 @@<br> int index = *resource_count;<br> <br> if (IS_ENABLED(CONFIG_SA_ENABLE_DPR))<br>- dpr_size = get_dpr_size();<br>+ dpr_size = sa_get_dpr_size();<br> <br> top_of_ram = (uintptr_t)cbmem_top();<br> <br>diff --git a/src/soc/intel/common/block/systemagent/systemagent_def.h b/src/soc/intel/common/block/systemagent/systemagent_def.h<br>index 29ce9ec..3243c85 100644<br>--- a/src/soc/intel/common/block/systemagent/systemagent_def.h<br>+++ b/src/soc/intel/common/block/systemagent/systemagent_def.h<br>@@ -19,6 +19,11 @@<br> <br> /* Device 0:0.0 PCI configuration space */<br> <br>+#define GGC 0x50 /* GMCH Graphics Control */<br>+#define G_GMS_OFFSET 0x8<br>+#define G_GMS_MASK 0xff00<br>+#define G_GGMS_OFFSET 0x6<br>+#define G_GGMS_MASK 0xc0<br> /* DPR register incase CONFIG_SA_ENABLE_DPR is selected by SoC */<br> #define DPR 0x5c<br> #define DPR_EPM (1 << 2)<br>diff --git a/src/soc/intel/common/block/systemagent/systemagent_early.c b/src/soc/intel/common/block/systemagent/systemagent_early.c<br>index 7cf78e7..7db907a 100644<br>--- a/src/soc/intel/common/block/systemagent/systemagent_early.c<br>+++ b/src/soc/intel/common/block/systemagent/systemagent_early.c<br>@@ -132,3 +132,69 @@<br> bios_reset_cpl |= 3;<br> MCHBAR8(BIOS_RESET_CPL) = bios_reset_cpl;<br> }<br>+<br>+uint32_t sa_get_tolud_base(void)<br>+{<br>+ /* All regions concerned for have 1 MiB alignment. */<br>+ return ALIGN_DOWN(pci_read_config32(SA_DEV_ROOT, TOLUD), 1*MiB);<br>+}<br>+<br>+static uint16_t sa_get_gcc_reg(void)<br>+{<br>+ uint16_t ggc;<br>+<br>+ ggc = pci_read_config32(SA_DEV_ROOT, GGC);<br>+<br>+ return ggc;<br>+}<br>+<br>+size_t sa_get_dsm_size(void)<br>+{<br>+ uint32_t dsm_size;<br>+<br>+ dsm_size = ((sa_get_gcc_reg() & G_GMS_MASK) >> G_GMS_OFFSET) * 32*MiB;<br>+<br>+ return dsm_size;<br>+}<br>+<br>+size_t sa_get_gsm_size(void)<br>+{<br>+ uint32_t gsm_size;<br>+<br>+ switch ((sa_get_gcc_reg() & G_GGMS_MASK) >> G_GGMS_OFFSET) {<br>+ case 1:<br>+ gsm_size = 2*MiB;<br>+ break;<br>+ case 2:<br>+ gsm_size = 4*MiB;<br>+ break;<br>+ case 3:<br>+ gsm_size = 8*MiB;<br>+ break;<br>+ default:<br>+ gsm_size = 0;<br>+ break;<br>+ }<br>+<br>+ return gsm_size;<br>+}<br>+<br>+/*<br>+ * Get DPR size incase CONFIG_SA_ENABLE_DPR is selected by SoC.<br>+ */<br>+size_t sa_get_dpr_size(void)<br>+{<br>+ uintptr_t dpr_reg;<br>+ size_t size = 0;<br>+ /*<br>+ * DMA Protected Range can be reserved below TSEG for PCODE patch<br>+ * or TXT/BootGuard related data. Rather than report a base address<br>+ * the DPR register reports the TOP of the region, which is the same<br>+ * as TSEG base. The region size is reported in MiB in bits 11:4.<br>+ */<br>+ dpr_reg = pci_read_config32(SA_DEV_ROOT, DPR);<br>+ if (dpr_reg & DPR_EPM)<br>+ size = (dpr_reg & DPR_SIZE_MASK) << 16;<br>+<br>+ return size;<br>+}<br></pre><p>To view, visit <a href="https://review.coreboot.org/21133">change 21133</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/21133"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I95250ef493c9844b8c46528f1f7de8a42cba88a2 </div>
<div style="display:none"> Gerrit-Change-Number: 21133 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Subrata Banik <subrata.banik@intel.com> </div>