[coreboot-gerrit] Change in coreboot[master]: [NOTFORMERGE, TESTONLY] Use MRC cache on Thinkpad X60
Arthur Heymans (Code Review)
gerrit at coreboot.org
Sun Aug 20 20:53:25 CEST 2017
Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/21114
Change subject: [NOTFORMERGE,TESTONLY] Use MRC cache on Thinkpad X60
......................................................................
[NOTFORMERGE,TESTONLY] Use MRC cache on Thinkpad X60
Just proof of concept.
Result: MRC cache gets properly written on a STT25VF016B.
Change-Id: I0b2d07727899a514d338d3cdbad04b7af4a16640
Signed-off-by: Arthur Heymans <arthur at aheymans.xyz>
---
M src/mainboard/lenovo/x60/romstage.c
M src/northbridge/intel/i945/Kconfig
M src/northbridge/intel/i945/Makefile.inc
M src/northbridge/intel/i945/early_init.c
M src/northbridge/intel/i945/i945.h
M src/northbridge/intel/i945/raminit.c
M src/northbridge/intel/i945/raminit.h
7 files changed, 75 insertions(+), 38 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/21114/1
diff --git a/src/mainboard/lenovo/x60/romstage.c b/src/mainboard/lenovo/x60/romstage.c
index eddb150..d332428 100644
--- a/src/mainboard/lenovo/x60/romstage.c
+++ b/src/mainboard/lenovo/x60/romstage.c
@@ -36,6 +36,7 @@
#include <northbridge/intel/i945/raminit.h>
#include <southbridge/intel/i82801gx/i82801gx.h>
#include <southbridge/intel/common/gpio.h>
+#include <delay.h>
#include "dock.h"
static void ich7_enable_lpc(void)
@@ -172,6 +173,7 @@
{
int s3resume = 0;
const u8 spd_addrmap[2 * DIMM_SOCKETS] = { 0x50, 0, 0x51, 0 };
+ struct sys_info sysinfo;
timestamp_init(get_initial_timestamp());
@@ -230,7 +232,7 @@
#endif
timestamp_add_now(TS_BEFORE_INITRAM);
- sdram_initialize(s3resume ? 2 : 0, spd_addrmap);
+ sdram_initialize(s3resume ? 2 : 0, spd_addrmap, &sysinfo);
timestamp_add_now(TS_AFTER_INITRAM);
/* Perform some initialization that must run before stage2 */
@@ -245,5 +247,5 @@
fixup_i945_errata();
/* Initialize the internal PCIe links before we go into stage2 */
- i945_late_initialization(s3resume);
+ i945_late_initialization(s3resume, &sysinfo);
}
diff --git a/src/northbridge/intel/i945/Kconfig b/src/northbridge/intel/i945/Kconfig
index 482f98a..0bbd96f 100644
--- a/src/northbridge/intel/i945/Kconfig
+++ b/src/northbridge/intel/i945/Kconfig
@@ -20,6 +20,7 @@
config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy
def_bool y
+ select NORTHBRIDGE_INTEL_COMMON_MRC_CACHE
select HAVE_DEBUG_RAM_SETUP
select LAPIC_MONOTONIC_TIMER
select VGA
@@ -87,4 +88,9 @@
On other boards the check always creates a false positive,
effectively making it impossible to resume.
+config MRC_CACHE_SIZE
+ hex
+ default 0x10000
+
+
endif
diff --git a/src/northbridge/intel/i945/Makefile.inc b/src/northbridge/intel/i945/Makefile.inc
index 0e4fcfc..24b8227 100644
--- a/src/northbridge/intel/i945/Makefile.inc
+++ b/src/northbridge/intel/i945/Makefile.inc
@@ -29,4 +29,14 @@
smm-y += udelay.c
+$(obj)/mrc.cache: $(obj)/config.h
+ dd if=/dev/zero count=1 \
+ bs=$(shell printf "%d" $(CONFIG_MRC_CACHE_SIZE) ) | \
+ tr '\000' '\377' > $@
+
+cbfs-files-y += mrc.cache
+mrc.cache-file := $(obj)/mrc.cache
+mrc.cache-align := 0x10000
+mrc.cache-type := mrc_cache
+
endif
diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c
index 1d473d3..f284b14 100644
--- a/src/northbridge/intel/i945/early_init.c
+++ b/src/northbridge/intel/i945/early_init.c
@@ -26,6 +26,9 @@
#include "i945.h"
#include <pc80/mc146818rtc.h>
#include <southbridge/intel/common/gpio.h>
+#include <northbridge/intel/common/mrc_cache.h>
+
+#include "raminit.h"
int i945_silicon_revision(void)
{
@@ -918,17 +921,18 @@
RCBA32(0x2010) |= (1 << 10);
}
-static void i945_prepare_resume(int s3resume)
+/* static void i945_prepare_resume(int s3resume) */
+/* { */
+/* int cbmem_was_initted; */
+
+/* cbmem_was_initted = !cbmem_recovery(s3resume); */
+
+/* romstage_handoff_init(cbmem_was_initted && s3resume); */
+/* } */
+
+void i945_late_initialization(int s3resume, struct sys_info *sysinfo)
{
int cbmem_was_initted;
-
- cbmem_was_initted = !cbmem_recovery(s3resume);
-
- romstage_handoff_init(cbmem_was_initted && s3resume);
-}
-
-void i945_late_initialization(int s3resume)
-{
i945_setup_egress_port();
ich7_setup_root_complex_topology();
@@ -963,5 +967,12 @@
MCHBAR16(SSKPD) = 0xCAFE;
- i945_prepare_resume(s3resume);
+ /* i945_prepare_resume(s3resume); */
+ cbmem_was_initted = !cbmem_recovery(s3resume);
+
+ if (!s3resume)
+ store_current_mrc_cache(sysinfo, sizeof(*sysinfo));
+
+ romstage_handoff_init(cbmem_was_initted && s3resume);
+
}
diff --git a/src/northbridge/intel/i945/i945.h b/src/northbridge/intel/i945/i945.h
index 330ace1..020cddf 100644
--- a/src/northbridge/intel/i945/i945.h
+++ b/src/northbridge/intel/i945/i945.h
@@ -352,7 +352,8 @@
int i945_silicon_revision(void);
void i945_early_initialization(void);
-void i945_late_initialization(int s3resume);
+#include "raminit.h"
+void i945_late_initialization(int s3resume, struct sys_info *sysinfo);
/* provided by mainboard code */
void setup_ich7_gpios(void);
diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c
index bd4a66d..d361568 100644
--- a/src/northbridge/intel/i945/raminit.c
+++ b/src/northbridge/intel/i945/raminit.c
@@ -30,6 +30,8 @@
#include "chip.h"
#include <cbmem.h>
#include <device/dram/ddr2.h>
+#include <northbridge/intel/common/mrc_cache.h>
+#include <delay.h>
/* Debugging macros. */
#if IS_ENABLED(CONFIG_DEBUG_RAM_SETUP)
@@ -2740,41 +2742,47 @@
* @param boot_path: 0 = normal, 1 = reset, 2 = resume from s3
* @param spd_addresses pointer to a list of SPD addresses
*/
-void sdram_initialize(int boot_path, const u8 *spd_addresses)
+void sdram_initialize(int boot_path, const u8 *spd_addresses, struct sys_info *sysinfo)
{
- struct sys_info sysinfo;
+ struct mrc_data_container *mrc_cache;
u8 reg8;
printk(BIOS_DEBUG, "Setting up RAM controller.\n");
- memset(&sysinfo, 0, sizeof(sysinfo));
+ memset(sysinfo, 0, sizeof(*sysinfo));
- sysinfo.boot_path = boot_path;
- sysinfo.spd_addresses = spd_addresses;
+ sysinfo->boot_path = boot_path;
+ sysinfo->spd_addresses = spd_addresses;
/* Look at the type of DIMMs and verify all DIMMs are x8 or x16 width */
- sdram_get_dram_configuration(&sysinfo);
+ sdram_get_dram_configuration(sysinfo);
+
+ if (boot_path == BOOT_PATH_RESUME) {
+ mrc_cache = find_current_mrc_cache();
+ memcpy(sysinfo, mrc_cache->mrc_data, sizeof(*sysinfo));
+ sysinfo->boot_path = boot_path;
+ }
/* If error, do cold boot */
- sdram_detect_errors(&sysinfo);
+ sdram_detect_errors(sysinfo);
/* Program PLL settings */
- sdram_program_pll_settings(&sysinfo);
+ sdram_program_pll_settings(sysinfo);
/*
* Program Graphics Frequency
* Set core display and render clock on 945GC to the max
*/
if (IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GM))
- sdram_program_graphics_frequency(&sysinfo);
+ sdram_program_graphics_frequency(sysinfo);
else
pci_write_config16(PCI_DEV(0, 2, 0), GCFC, 0x0534);
/* Program System Memory Frequency */
- sdram_program_memory_frequency(&sysinfo);
+ sdram_program_memory_frequency(sysinfo);
/* Determine Mode of Operation (Interleaved etc) */
- sdram_set_channel_mode(&sysinfo);
+ sdram_set_channel_mode(sysinfo);
/* Program Clock Crossing values */
sdram_program_clock_crossing();
@@ -2789,42 +2797,42 @@
/* Program DRAM Row Boundary/Attribute Registers */
/* program row size DRB and set TOLUD */
- sdram_program_row_boundaries(&sysinfo);
+ sdram_program_row_boundaries(sysinfo);
/* program page size DRA */
- sdram_set_row_attributes(&sysinfo);
+ sdram_set_row_attributes(sysinfo);
/* Program CxBNKARC */
- sdram_set_bank_architecture(&sysinfo);
+ sdram_set_bank_architecture(sysinfo);
/* Program DRAM Timing and Control registers based on SPD */
- sdram_set_timing_and_control(&sysinfo);
+ sdram_set_timing_and_control(sysinfo);
/* On-Die Termination Adjustment */
- sdram_on_die_termination(&sysinfo);
+ sdram_on_die_termination(sysinfo);
/* Pre Jedec Initialization */
sdram_pre_jedec_initialization();
/* Perform System Memory IO Initialization */
- sdram_initialize_system_memory_io(&sysinfo);
+ sdram_initialize_system_memory_io(sysinfo);
/* Perform System Memory IO Buffer Enable */
- sdram_enable_system_memory_io(&sysinfo);
+ sdram_enable_system_memory_io(sysinfo);
/* Enable System Memory Clocks */
- sdram_enable_memory_clocks(&sysinfo);
+ sdram_enable_memory_clocks(sysinfo);
if (boot_path == BOOT_PATH_NORMAL) {
/* Jedec Initialization sequence */
- sdram_jedec_enable(&sysinfo);
+ sdram_jedec_enable(sysinfo);
}
/* Program Power Management Registers */
- sdram_power_management(&sysinfo);
+ sdram_power_management(sysinfo);
/* Post Jedec Init */
- sdram_post_jedec_initialization(&sysinfo);
+ sdram_post_jedec_initialization(sysinfo);
/* Program DRAM Throttling */
sdram_thermal_management();
@@ -2833,7 +2841,7 @@
sdram_init_complete();
/* Program Receive Enable Timings */
- sdram_program_receive_enable(&sysinfo);
+ sdram_program_receive_enable(sysinfo);
/* Enable Periodic RCOMP */
sdram_enable_rcomp();
diff --git a/src/northbridge/intel/i945/raminit.h b/src/northbridge/intel/i945/raminit.h
index 7d85557..974abc3 100644
--- a/src/northbridge/intel/i945/raminit.h
+++ b/src/northbridge/intel/i945/raminit.h
@@ -68,9 +68,8 @@
} __packed;
void receive_enable_adjust(struct sys_info *sysinfo);
-void sdram_initialize(int boot_path, const u8 *sdram_addresses);
+void sdram_initialize(int boot_path, const u8 *spd_addresses, struct sys_info *sysinfo);
int fixup_i945_errata(void);
-void udelay(u32 us);
#if IS_ENABLED(CONFIG_DEBUG_RAM_SETUP)
void sdram_dump_mchbar_registers(void);
--
To view, visit https://review.coreboot.org/21114
To unsubscribe, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I0b2d07727899a514d338d3cdbad04b7af4a16640
Gerrit-Change-Number: 21114
Gerrit-PatchSet: 1
Gerrit-Owner: Arthur Heymans <arthur at aheymans.xyz>
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