<p>Arthur Heymans has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/21114">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">[NOTFORMERGE,TESTONLY] Use MRC cache on Thinkpad X60<br><br>Just proof of concept.<br>Result: MRC cache gets properly written on a STT25VF016B.<br><br>Change-Id: I0b2d07727899a514d338d3cdbad04b7af4a16640<br>Signed-off-by: Arthur Heymans <arthur@aheymans.xyz><br>---<br>M src/mainboard/lenovo/x60/romstage.c<br>M src/northbridge/intel/i945/Kconfig<br>M src/northbridge/intel/i945/Makefile.inc<br>M src/northbridge/intel/i945/early_init.c<br>M src/northbridge/intel/i945/i945.h<br>M src/northbridge/intel/i945/raminit.c<br>M src/northbridge/intel/i945/raminit.h<br>7 files changed, 75 insertions(+), 38 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/21114/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/mainboard/lenovo/x60/romstage.c b/src/mainboard/lenovo/x60/romstage.c<br>index eddb150..d332428 100644<br>--- a/src/mainboard/lenovo/x60/romstage.c<br>+++ b/src/mainboard/lenovo/x60/romstage.c<br>@@ -36,6 +36,7 @@<br> #include <northbridge/intel/i945/raminit.h><br> #include <southbridge/intel/i82801gx/i82801gx.h><br> #include <southbridge/intel/common/gpio.h><br>+#include <delay.h><br> #include "dock.h"<br> <br> static void ich7_enable_lpc(void)<br>@@ -172,6 +173,7 @@<br> {<br> int s3resume = 0;<br> const u8 spd_addrmap[2 * DIMM_SOCKETS] = { 0x50, 0, 0x51, 0 };<br>+ struct sys_info sysinfo;<br> <br> <br> timestamp_init(get_initial_timestamp());<br>@@ -230,7 +232,7 @@<br> #endif<br> <br> timestamp_add_now(TS_BEFORE_INITRAM);<br>- sdram_initialize(s3resume ? 2 : 0, spd_addrmap);<br>+ sdram_initialize(s3resume ? 2 : 0, spd_addrmap, &sysinfo);<br> timestamp_add_now(TS_AFTER_INITRAM);<br> <br> /* Perform some initialization that must run before stage2 */<br>@@ -245,5 +247,5 @@<br> fixup_i945_errata();<br> <br> /* Initialize the internal PCIe links before we go into stage2 */<br>- i945_late_initialization(s3resume);<br>+ i945_late_initialization(s3resume, &sysinfo);<br> }<br>diff --git a/src/northbridge/intel/i945/Kconfig b/src/northbridge/intel/i945/Kconfig<br>index 482f98a..0bbd96f 100644<br>--- a/src/northbridge/intel/i945/Kconfig<br>+++ b/src/northbridge/intel/i945/Kconfig<br>@@ -20,6 +20,7 @@<br> <br> config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy<br> def_bool y<br>+ select NORTHBRIDGE_INTEL_COMMON_MRC_CACHE<br> select HAVE_DEBUG_RAM_SETUP<br> select LAPIC_MONOTONIC_TIMER<br> select VGA<br>@@ -87,4 +88,9 @@<br> On other boards the check always creates a false positive,<br> effectively making it impossible to resume.<br> <br>+config MRC_CACHE_SIZE<br>+ hex<br>+ default 0x10000<br>+<br>+<br> endif<br>diff --git a/src/northbridge/intel/i945/Makefile.inc b/src/northbridge/intel/i945/Makefile.inc<br>index 0e4fcfc..24b8227 100644<br>--- a/src/northbridge/intel/i945/Makefile.inc<br>+++ b/src/northbridge/intel/i945/Makefile.inc<br>@@ -29,4 +29,14 @@<br> <br> smm-y += udelay.c<br> <br>+$(obj)/mrc.cache: $(obj)/config.h<br>+ dd if=/dev/zero count=1 \<br>+ bs=$(shell printf "%d" $(CONFIG_MRC_CACHE_SIZE) ) | \<br>+ tr '\000' '\377' > $@<br>+<br>+cbfs-files-y += mrc.cache<br>+mrc.cache-file := $(obj)/mrc.cache<br>+mrc.cache-align := 0x10000<br>+mrc.cache-type := mrc_cache<br>+<br> endif<br>diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c<br>index 1d473d3..f284b14 100644<br>--- a/src/northbridge/intel/i945/early_init.c<br>+++ b/src/northbridge/intel/i945/early_init.c<br>@@ -26,6 +26,9 @@<br> #include "i945.h"<br> #include <pc80/mc146818rtc.h><br> #include <southbridge/intel/common/gpio.h><br>+#include <northbridge/intel/common/mrc_cache.h><br>+<br>+#include "raminit.h"<br> <br> int i945_silicon_revision(void)<br> {<br>@@ -918,17 +921,18 @@<br> RCBA32(0x2010) |= (1 << 10);<br> }<br> <br>-static void i945_prepare_resume(int s3resume)<br>+/* static void i945_prepare_resume(int s3resume) */<br>+/* { */<br>+/* int cbmem_was_initted; */<br>+<br>+/* cbmem_was_initted = !cbmem_recovery(s3resume); */<br>+<br>+/* romstage_handoff_init(cbmem_was_initted && s3resume); */<br>+/* } */<br>+<br>+void i945_late_initialization(int s3resume, struct sys_info *sysinfo)<br> {<br> int cbmem_was_initted;<br>-<br>- cbmem_was_initted = !cbmem_recovery(s3resume);<br>-<br>- romstage_handoff_init(cbmem_was_initted && s3resume);<br>-}<br>-<br>-void i945_late_initialization(int s3resume)<br>-{<br> i945_setup_egress_port();<br> <br> ich7_setup_root_complex_topology();<br>@@ -963,5 +967,12 @@<br> <br> MCHBAR16(SSKPD) = 0xCAFE;<br> <br>- i945_prepare_resume(s3resume);<br>+ /* i945_prepare_resume(s3resume); */<br>+ cbmem_was_initted = !cbmem_recovery(s3resume);<br>+<br>+ if (!s3resume)<br>+ store_current_mrc_cache(sysinfo, sizeof(*sysinfo));<br>+ <br>+ romstage_handoff_init(cbmem_was_initted && s3resume);<br>+<br> }<br>diff --git a/src/northbridge/intel/i945/i945.h b/src/northbridge/intel/i945/i945.h<br>index 330ace1..020cddf 100644<br>--- a/src/northbridge/intel/i945/i945.h<br>+++ b/src/northbridge/intel/i945/i945.h<br>@@ -352,7 +352,8 @@<br> <br> int i945_silicon_revision(void);<br> void i945_early_initialization(void);<br>-void i945_late_initialization(int s3resume);<br>+#include "raminit.h"<br>+void i945_late_initialization(int s3resume, struct sys_info *sysinfo);<br> <br> /* provided by mainboard code */<br> void setup_ich7_gpios(void);<br>diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c<br>index bd4a66d..d361568 100644<br>--- a/src/northbridge/intel/i945/raminit.c<br>+++ b/src/northbridge/intel/i945/raminit.c<br>@@ -30,6 +30,8 @@<br> #include "chip.h"<br> #include <cbmem.h><br> #include <device/dram/ddr2.h><br>+#include <northbridge/intel/common/mrc_cache.h><br>+#include <delay.h><br> <br> /* Debugging macros. */<br> #if IS_ENABLED(CONFIG_DEBUG_RAM_SETUP)<br>@@ -2740,41 +2742,47 @@<br> * @param boot_path: 0 = normal, 1 = reset, 2 = resume from s3<br> * @param spd_addresses pointer to a list of SPD addresses<br> */<br>-void sdram_initialize(int boot_path, const u8 *spd_addresses)<br>+void sdram_initialize(int boot_path, const u8 *spd_addresses, struct sys_info *sysinfo)<br> {<br>- struct sys_info sysinfo;<br>+ struct mrc_data_container *mrc_cache;<br> u8 reg8;<br> <br> printk(BIOS_DEBUG, "Setting up RAM controller.\n");<br> <br>- memset(&sysinfo, 0, sizeof(sysinfo));<br>+ memset(sysinfo, 0, sizeof(*sysinfo));<br> <br>- sysinfo.boot_path = boot_path;<br>- sysinfo.spd_addresses = spd_addresses;<br>+ sysinfo->boot_path = boot_path;<br>+ sysinfo->spd_addresses = spd_addresses;<br> <br> /* Look at the type of DIMMs and verify all DIMMs are x8 or x16 width */<br>- sdram_get_dram_configuration(&sysinfo);<br>+ sdram_get_dram_configuration(sysinfo);<br>+<br>+ if (boot_path == BOOT_PATH_RESUME) {<br>+ mrc_cache = find_current_mrc_cache();<br>+ memcpy(sysinfo, mrc_cache->mrc_data, sizeof(*sysinfo));<br>+ sysinfo->boot_path = boot_path;<br>+ }<br> <br> /* If error, do cold boot */<br>- sdram_detect_errors(&sysinfo);<br>+ sdram_detect_errors(sysinfo);<br> <br> /* Program PLL settings */<br>- sdram_program_pll_settings(&sysinfo);<br>+ sdram_program_pll_settings(sysinfo);<br> <br> /*<br> * Program Graphics Frequency<br> * Set core display and render clock on 945GC to the max<br> */<br> if (IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GM))<br>- sdram_program_graphics_frequency(&sysinfo);<br>+ sdram_program_graphics_frequency(sysinfo);<br> else<br> pci_write_config16(PCI_DEV(0, 2, 0), GCFC, 0x0534);<br> <br> /* Program System Memory Frequency */<br>- sdram_program_memory_frequency(&sysinfo);<br>+ sdram_program_memory_frequency(sysinfo);<br> <br> /* Determine Mode of Operation (Interleaved etc) */<br>- sdram_set_channel_mode(&sysinfo);<br>+ sdram_set_channel_mode(sysinfo);<br> <br> /* Program Clock Crossing values */<br> sdram_program_clock_crossing();<br>@@ -2789,42 +2797,42 @@<br> /* Program DRAM Row Boundary/Attribute Registers */<br> <br> /* program row size DRB and set TOLUD */<br>- sdram_program_row_boundaries(&sysinfo);<br>+ sdram_program_row_boundaries(sysinfo);<br> <br> /* program page size DRA */<br>- sdram_set_row_attributes(&sysinfo);<br>+ sdram_set_row_attributes(sysinfo);<br> <br> /* Program CxBNKARC */<br>- sdram_set_bank_architecture(&sysinfo);<br>+ sdram_set_bank_architecture(sysinfo);<br> <br> /* Program DRAM Timing and Control registers based on SPD */<br>- sdram_set_timing_and_control(&sysinfo);<br>+ sdram_set_timing_and_control(sysinfo);<br> <br> /* On-Die Termination Adjustment */<br>- sdram_on_die_termination(&sysinfo);<br>+ sdram_on_die_termination(sysinfo);<br> <br> /* Pre Jedec Initialization */<br> sdram_pre_jedec_initialization();<br> <br> /* Perform System Memory IO Initialization */<br>- sdram_initialize_system_memory_io(&sysinfo);<br>+ sdram_initialize_system_memory_io(sysinfo);<br> <br> /* Perform System Memory IO Buffer Enable */<br>- sdram_enable_system_memory_io(&sysinfo);<br>+ sdram_enable_system_memory_io(sysinfo);<br> <br> /* Enable System Memory Clocks */<br>- sdram_enable_memory_clocks(&sysinfo);<br>+ sdram_enable_memory_clocks(sysinfo);<br> <br> if (boot_path == BOOT_PATH_NORMAL) {<br> /* Jedec Initialization sequence */<br>- sdram_jedec_enable(&sysinfo);<br>+ sdram_jedec_enable(sysinfo);<br> }<br> <br> /* Program Power Management Registers */<br>- sdram_power_management(&sysinfo);<br>+ sdram_power_management(sysinfo);<br> <br> /* Post Jedec Init */<br>- sdram_post_jedec_initialization(&sysinfo);<br>+ sdram_post_jedec_initialization(sysinfo);<br> <br> /* Program DRAM Throttling */<br> sdram_thermal_management();<br>@@ -2833,7 +2841,7 @@<br> sdram_init_complete();<br> <br> /* Program Receive Enable Timings */<br>- sdram_program_receive_enable(&sysinfo);<br>+ sdram_program_receive_enable(sysinfo);<br> <br> /* Enable Periodic RCOMP */<br> sdram_enable_rcomp();<br>diff --git a/src/northbridge/intel/i945/raminit.h b/src/northbridge/intel/i945/raminit.h<br>index 7d85557..974abc3 100644<br>--- a/src/northbridge/intel/i945/raminit.h<br>+++ b/src/northbridge/intel/i945/raminit.h<br>@@ -68,9 +68,8 @@<br> } __packed;<br> <br> void receive_enable_adjust(struct sys_info *sysinfo);<br>-void sdram_initialize(int boot_path, const u8 *sdram_addresses);<br>+void sdram_initialize(int boot_path, const u8 *spd_addresses, struct sys_info *sysinfo);<br> int fixup_i945_errata(void);<br>-void udelay(u32 us);<br> <br> #if IS_ENABLED(CONFIG_DEBUG_RAM_SETUP)<br> void sdram_dump_mchbar_registers(void);<br></pre><p>To view, visit <a href="https://review.coreboot.org/21114">change 21114</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/21114"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I0b2d07727899a514d338d3cdbad04b7af4a16640 </div>
<div style="display:none"> Gerrit-Change-Number: 21114 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Arthur Heymans <arthur@aheymans.xyz> </div>