[coreboot-gerrit] Change in coreboot[master]: sb/intel/common/spi.c: Port to i82801gx

[Arthur Heymans (Code Review)]

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/21113


Change subject: sb/intel/common/spi.c: Port to i82801gx
......................................................................

sb/intel/common/spi.c: Port to i82801gx

Offsets are a little different.

TESTED on Thinkpad X60

Change-Id: I39199f3279a8b76e290b6693adc50dc2ac0ccf23
Signed-off-by: Arthur Heymans <arthur at aheymans.xyz>
---
M src/southbridge/intel/common/spi.c
M src/southbridge/intel/i82801gx/Kconfig
M src/southbridge/intel/i82801gx/Makefile.inc
3 files changed, 40 insertions(+), 18 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/21113/1

diff --git a/src/southbridge/intel/common/spi.c b/src/southbridge/intel/common/spi.c
index a6a9ae5..52fdd4f 100644
--- a/src/southbridge/intel/common/spi.c
+++ b/src/southbridge/intel/common/spi.c
@@ -124,6 +124,7 @@
 	uint32_t hsfs;
 
 	ich9_spi_regs *ich9_spi;
+	ich7_spi_regs *ich7_spi;
 	uint8_t *opmenu;
 	int menubytes;
 	uint16_t *preop;
@@ -294,6 +295,7 @@
 	uint8_t bios_cntl;
 	device_t dev;
 	ich9_spi_regs *ich9_spi;
+	ich7_spi_regs *ich7_spi;
 	uint16_t hsfs;
 
 #ifdef __SMM__
@@ -305,23 +307,39 @@
 	pci_read_config_dword(dev, 0xf0, &rcba);
 	/* Bits 31-14 are the base address, 13-1 are reserved, 0 is enable. */
 	rcrb = (uint8_t *)(rcba & 0xffffc000);
-	ich9_spi = (ich9_spi_regs *)(rcrb + 0x3800);
-	cntlr.ich9_spi = ich9_spi;
-	hsfs = readw_(&ich9_spi->hsfs);
-	ichspi_lock = hsfs & HSFS_FLOCKDN;
-	cntlr.hsfs = hsfs;
-	cntlr.opmenu = ich9_spi->opmenu;
-	cntlr.menubytes = sizeof(ich9_spi->opmenu);
-	cntlr.optype = &ich9_spi->optype;
-	cntlr.addr = &ich9_spi->faddr;
-	cntlr.data = (uint8_t *)ich9_spi->fdata;
-	cntlr.databytes = sizeof(ich9_spi->fdata);
-	cntlr.status = &ich9_spi->ssfs;
-	cntlr.control = (uint16_t *)ich9_spi->ssfc;
-	cntlr.bbar = &ich9_spi->bbar;
-	cntlr.preop = &ich9_spi->preop;
+	if (IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_I82801GX)) {
+		ich7_spi = (ich7_spi_regs *)(rcrb + 0x3020);
+		cntlr.ich7_spi = ich7_spi;		
+		cntlr.opmenu = ich7_spi->opmenu;
+		cntlr.menubytes = sizeof(ich7_spi->opmenu);
+		cntlr.optype = &ich7_spi->optype;
+		cntlr.addr = &ich7_spi->spia; /* ?? */
+		cntlr.data = (uint8_t *)ich7_spi->spid;
+		cntlr.databytes = sizeof(ich7_spi->spid);
+		cntlr.status = (uint8_t *)&ich7_spi->spis;
+		ichspi_lock = ich7_spi->spis & HSFS_FLOCKDN;
+		cntlr.control = &ich7_spi->spic;
+		cntlr.bbar = &ich7_spi->bbar;
+		cntlr.preop = &ich7_spi->preop;
+	} else {
+		ich9_spi = (ich9_spi_regs *)(rcrb + 0x3800);	
+		cntlr.ich9_spi = ich9_spi;
+		hsfs = readw_(&ich9_spi->hsfs);
+		ichspi_lock = hsfs & HSFS_FLOCKDN;
+		cntlr.hsfs = hsfs;
+		cntlr.opmenu = ich9_spi->opmenu;
+		cntlr.menubytes = sizeof(ich9_spi->opmenu);
+		cntlr.optype = &ich9_spi->optype;
+		cntlr.addr = &ich9_spi->faddr;
+		cntlr.data = (uint8_t *)ich9_spi->fdata;
+		cntlr.databytes = sizeof(ich9_spi->fdata);
+		cntlr.status = &ich9_spi->ssfs;
+		cntlr.control = (uint16_t *)ich9_spi->ssfc;
+		cntlr.bbar = &ich9_spi->bbar;
+		cntlr.preop = &ich9_spi->preop;
+	}
 
-	if (cntlr.hsfs & HSFS_FDV)
+	if ((cntlr.hsfs & HSFS_FDV) && !IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_I82801GX))
 	{
 		writel_ (4, &ich9_spi->fdoc);
 		cntlr.flmap0 = readl_(&ich9_spi->fdod);
@@ -657,8 +675,10 @@
 /* Sets FLA in FADDR to (addr & 0x01FFFFFF) without touching other bits. */
 static void ich_hwseq_set_addr(uint32_t addr)
 {
-	uint32_t addr_old = readl_(&cntlr.ich9_spi->faddr) & ~0x01FFFFFF;
-	writel_((addr & 0x01FFFFFF) | addr_old, &cntlr.ich9_spi->faddr);
+	u32 mask = IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_I82801GX) ? 0x00ffffff
+		: 0x01ffffff; 
+	uint32_t addr_old = readl_(cntlr.addr) & ~mask;
+	writel_((addr & mask) | addr_old, cntlr.addr);
 }
 
 /* Polls for Cycle Done Status, Flash Cycle Error or timeout in 8 us intervals.
diff --git a/src/southbridge/intel/i82801gx/Kconfig b/src/southbridge/intel/i82801gx/Kconfig
index 68c2362..fd7579a 100644
--- a/src/southbridge/intel/i82801gx/Kconfig
+++ b/src/southbridge/intel/i82801gx/Kconfig
@@ -23,6 +23,7 @@
 	select USE_WATCHDOG_ON_BOOT
 	select HAVE_SMI_HANDLER
 	select COMMON_FADT
+	select SPI_FLASH
 	select SOUTHBRIDGE_INTEL_COMMON_GPIO
 	select SOUTHBRIDGE_INTEL_COMMON_SMBUS
 
diff --git a/src/southbridge/intel/i82801gx/Makefile.inc b/src/southbridge/intel/i82801gx/Makefile.inc
index bb68d93..5b3ba6a 100644
--- a/src/southbridge/intel/i82801gx/Makefile.inc
+++ b/src/southbridge/intel/i82801gx/Makefile.inc
@@ -27,6 +27,7 @@
 ramstage-y += smbus.c
 ramstage-y += usb.c
 ramstage-y += usb_ehci.c
+ramstage-y += ../common/spi.c
 
 ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/hda_verb.c
 

-- 
To view, visit https://review.coreboot.org/21113
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I39199f3279a8b76e290b6693adc50dc2ac0ccf23
Gerrit-Change-Number: 21113
Gerrit-PatchSet: 1
Gerrit-Owner: Arthur Heymans <arthur at aheymans.xyz>
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