<p>Arthur Heymans has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/21113">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">sb/intel/common/spi.c: Port to i82801gx<br><br>Offsets are a little different.<br><br>TESTED on Thinkpad X60<br><br>Change-Id: I39199f3279a8b76e290b6693adc50dc2ac0ccf23<br>Signed-off-by: Arthur Heymans <arthur@aheymans.xyz><br>---<br>M src/southbridge/intel/common/spi.c<br>M src/southbridge/intel/i82801gx/Kconfig<br>M src/southbridge/intel/i82801gx/Makefile.inc<br>3 files changed, 40 insertions(+), 18 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/21113/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/southbridge/intel/common/spi.c b/src/southbridge/intel/common/spi.c<br>index a6a9ae5..52fdd4f 100644<br>--- a/src/southbridge/intel/common/spi.c<br>+++ b/src/southbridge/intel/common/spi.c<br>@@ -124,6 +124,7 @@<br> uint32_t hsfs;<br> <br> ich9_spi_regs *ich9_spi;<br>+ ich7_spi_regs *ich7_spi;<br> uint8_t *opmenu;<br> int menubytes;<br> uint16_t *preop;<br>@@ -294,6 +295,7 @@<br> uint8_t bios_cntl;<br> device_t dev;<br> ich9_spi_regs *ich9_spi;<br>+ ich7_spi_regs *ich7_spi;<br> uint16_t hsfs;<br> <br> #ifdef __SMM__<br>@@ -305,23 +307,39 @@<br> pci_read_config_dword(dev, 0xf0, &rcba);<br> /* Bits 31-14 are the base address, 13-1 are reserved, 0 is enable. */<br> rcrb = (uint8_t *)(rcba & 0xffffc000);<br>- ich9_spi = (ich9_spi_regs *)(rcrb + 0x3800);<br>- cntlr.ich9_spi = ich9_spi;<br>- hsfs = readw_(&ich9_spi->hsfs);<br>- ichspi_lock = hsfs & HSFS_FLOCKDN;<br>- cntlr.hsfs = hsfs;<br>- cntlr.opmenu = ich9_spi->opmenu;<br>- cntlr.menubytes = sizeof(ich9_spi->opmenu);<br>- cntlr.optype = &ich9_spi->optype;<br>- cntlr.addr = &ich9_spi->faddr;<br>- cntlr.data = (uint8_t *)ich9_spi->fdata;<br>- cntlr.databytes = sizeof(ich9_spi->fdata);<br>- cntlr.status = &ich9_spi->ssfs;<br>- cntlr.control = (uint16_t *)ich9_spi->ssfc;<br>- cntlr.bbar = &ich9_spi->bbar;<br>- cntlr.preop = &ich9_spi->preop;<br>+ if (IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_I82801GX)) {<br>+ ich7_spi = (ich7_spi_regs *)(rcrb + 0x3020);<br>+ cntlr.ich7_spi = ich7_spi; <br>+ cntlr.opmenu = ich7_spi->opmenu;<br>+ cntlr.menubytes = sizeof(ich7_spi->opmenu);<br>+ cntlr.optype = &ich7_spi->optype;<br>+ cntlr.addr = &ich7_spi->spia; /* ?? */<br>+ cntlr.data = (uint8_t *)ich7_spi->spid;<br>+ cntlr.databytes = sizeof(ich7_spi->spid);<br>+ cntlr.status = (uint8_t *)&ich7_spi->spis;<br>+ ichspi_lock = ich7_spi->spis & HSFS_FLOCKDN;<br>+ cntlr.control = &ich7_spi->spic;<br>+ cntlr.bbar = &ich7_spi->bbar;<br>+ cntlr.preop = &ich7_spi->preop;<br>+ } else {<br>+ ich9_spi = (ich9_spi_regs *)(rcrb + 0x3800); <br>+ cntlr.ich9_spi = ich9_spi;<br>+ hsfs = readw_(&ich9_spi->hsfs);<br>+ ichspi_lock = hsfs & HSFS_FLOCKDN;<br>+ cntlr.hsfs = hsfs;<br>+ cntlr.opmenu = ich9_spi->opmenu;<br>+ cntlr.menubytes = sizeof(ich9_spi->opmenu);<br>+ cntlr.optype = &ich9_spi->optype;<br>+ cntlr.addr = &ich9_spi->faddr;<br>+ cntlr.data = (uint8_t *)ich9_spi->fdata;<br>+ cntlr.databytes = sizeof(ich9_spi->fdata);<br>+ cntlr.status = &ich9_spi->ssfs;<br>+ cntlr.control = (uint16_t *)ich9_spi->ssfc;<br>+ cntlr.bbar = &ich9_spi->bbar;<br>+ cntlr.preop = &ich9_spi->preop;<br>+ }<br> <br>- if (cntlr.hsfs & HSFS_FDV)<br>+ if ((cntlr.hsfs & HSFS_FDV) && !IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_I82801GX))<br> {<br> writel_ (4, &ich9_spi->fdoc);<br> cntlr.flmap0 = readl_(&ich9_spi->fdod);<br>@@ -657,8 +675,10 @@<br> /* Sets FLA in FADDR to (addr & 0x01FFFFFF) without touching other bits. */<br> static void ich_hwseq_set_addr(uint32_t addr)<br> {<br>- uint32_t addr_old = readl_(&cntlr.ich9_spi->faddr) & ~0x01FFFFFF;<br>- writel_((addr & 0x01FFFFFF) | addr_old, &cntlr.ich9_spi->faddr);<br>+ u32 mask = IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_I82801GX) ? 0x00ffffff<br>+ : 0x01ffffff; <br>+ uint32_t addr_old = readl_(cntlr.addr) & ~mask;<br>+ writel_((addr & mask) | addr_old, cntlr.addr);<br> }<br> <br> /* Polls for Cycle Done Status, Flash Cycle Error or timeout in 8 us intervals.<br>diff --git a/src/southbridge/intel/i82801gx/Kconfig b/src/southbridge/intel/i82801gx/Kconfig<br>index 68c2362..fd7579a 100644<br>--- a/src/southbridge/intel/i82801gx/Kconfig<br>+++ b/src/southbridge/intel/i82801gx/Kconfig<br>@@ -23,6 +23,7 @@<br> select USE_WATCHDOG_ON_BOOT<br> select HAVE_SMI_HANDLER<br> select COMMON_FADT<br>+ select SPI_FLASH<br> select SOUTHBRIDGE_INTEL_COMMON_GPIO<br> select SOUTHBRIDGE_INTEL_COMMON_SMBUS<br> <br>diff --git a/src/southbridge/intel/i82801gx/Makefile.inc b/src/southbridge/intel/i82801gx/Makefile.inc<br>index bb68d93..5b3ba6a 100644<br>--- a/src/southbridge/intel/i82801gx/Makefile.inc<br>+++ b/src/southbridge/intel/i82801gx/Makefile.inc<br>@@ -27,6 +27,7 @@<br> ramstage-y += smbus.c<br> ramstage-y += usb.c<br> ramstage-y += usb_ehci.c<br>+ramstage-y += ../common/spi.c<br> <br> ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/hda_verb.c<br> <br></pre><p>To view, visit <a href="https://review.coreboot.org/21113">change 21113</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/21113"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I39199f3279a8b76e290b6693adc50dc2ac0ccf23 </div>
<div style="display:none"> Gerrit-Change-Number: 21113 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Arthur Heymans <arthur@aheymans.xyz> </div>