[coreboot-gerrit] Change in coreboot[master]: soc/braswell/lpe: add resource allocation for BAR1

[Matt DeVillier (Code Review)]

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/21103


Change subject: soc/braswell/lpe: add resource allocation for BAR1
......................................................................

soc/braswell/lpe: add resource allocation for BAR1

coreboot's PCI resource allocator doesn't assign BAR1 for
Braswell's LPE device, possibly because it's located where
coreboot typically assigns BAR2 (0x18).
Manually add the required resource via the existing
lpe_read_resources function.

TEST: boot google/cyan, observe MMIO values at BAR1 match
expected values per datasheet (#332066-002)

Change-Id: Iaa68319da5fb999fe8d73792eaee692cce60c8a2
Signed-off-by: Matt DeVillier <matt.devillier at gmail.com>
---
M src/soc/intel/braswell/lpe.c
1 file changed, 10 insertions(+), 2 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/21103/1

diff --git a/src/soc/intel/braswell/lpe.c b/src/soc/intel/braswell/lpe.c
index 58b5a8d..fe3fe9e 100644
--- a/src/soc/intel/braswell/lpe.c
+++ b/src/soc/intel/braswell/lpe.c
@@ -77,8 +77,7 @@
 
 	/* Save BAR0, BAR1, and firmware base  to ACPI NVS */
 	assign_device_nvs(dev, &gnvs->dev.lpe_bar0, PCI_BASE_ADDRESS_0);
-	/* LPE seems does not have BAR at PCI_BASE_ADDRESS_1 so disable it. */
-	/* assign_device_nvs(dev, &gnvs->dev.lpe_bar1, PCI_BASE_ADDRESS_1);  */
+	assign_device_nvs(dev, &gnvs->dev.lpe_bar1, PCI_BASE_ADDRESS_2);
 	assign_device_nvs(dev, &gnvs->dev.lpe_fw, FIRMWARE_PCI_REG_BASE);
 
 	/* Device is enabled in ACPI mode */
@@ -165,8 +164,17 @@
 
 static void lpe_read_resources(device_t dev)
 {
+	struct resource *res;
 	pci_dev_read_resources(dev);
 
+	res = new_resource(dev, PCI_BASE_ADDRESS_2);
+	res->base = 0;
+	res->size = 0x1000;
+	res->limit = 0xffffffff;
+	res->gran = 0x0c;
+	res->align = 0x0c;
+	res->flags = IORESOURCE_MEM;
+
 	reserved_ram_resource(dev, FIRMWARE_PCI_REG_BASE,
 			      FIRMWARE_PHYS_BASE >> 10,
 			      FIRMWARE_PHYS_LENGTH >> 10);

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Iaa68319da5fb999fe8d73792eaee692cce60c8a2
Gerrit-Change-Number: 21103
Gerrit-PatchSet: 1
Gerrit-Owner: Matt DeVillier <matt.devillier at gmail.com>
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