<p>Matt DeVillier has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/21103">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/braswell/lpe: add resource allocation for BAR1<br><br>coreboot's PCI resource allocator doesn't assign BAR1 for<br>Braswell's LPE device, possibly because it's located where<br>coreboot typically assigns BAR2 (0x18).<br>Manually add the required resource via the existing<br>lpe_read_resources function.<br><br>TEST: boot google/cyan, observe MMIO values at BAR1 match<br>expected values per datasheet (#332066-002)<br><br>Change-Id: Iaa68319da5fb999fe8d73792eaee692cce60c8a2<br>Signed-off-by: Matt DeVillier <matt.devillier@gmail.com><br>---<br>M src/soc/intel/braswell/lpe.c<br>1 file changed, 10 insertions(+), 2 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/21103/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/soc/intel/braswell/lpe.c b/src/soc/intel/braswell/lpe.c<br>index 58b5a8d..fe3fe9e 100644<br>--- a/src/soc/intel/braswell/lpe.c<br>+++ b/src/soc/intel/braswell/lpe.c<br>@@ -77,8 +77,7 @@<br> <br>   /* Save BAR0, BAR1, and firmware base  to ACPI NVS */<br>         assign_device_nvs(dev, &gnvs->dev.lpe_bar0, PCI_BASE_ADDRESS_0);<br>-      /* LPE seems does not have BAR at PCI_BASE_ADDRESS_1 so disable it. */<br>-       /* assign_device_nvs(dev, &gnvs->dev.lpe_bar1, PCI_BASE_ADDRESS_1);  */<br>+       assign_device_nvs(dev, &gnvs->dev.lpe_bar1, PCI_BASE_ADDRESS_2);<br>       assign_device_nvs(dev, &gnvs->dev.lpe_fw, FIRMWARE_PCI_REG_BASE);<br> <br>   /* Device is enabled in ACPI mode */<br>@@ -165,8 +164,17 @@<br> <br> static void lpe_read_resources(device_t dev)<br> {<br>+     struct resource *res;<br>         pci_dev_read_resources(dev);<br> <br>+      res = new_resource(dev, PCI_BASE_ADDRESS_2);<br>+ res->base = 0;<br>+    res->size = 0x1000;<br>+       res->limit = 0xffffffff;<br>+  res->gran = 0x0c;<br>+ res->align = 0x0c;<br>+        res->flags = IORESOURCE_MEM;<br>+<br>    reserved_ram_resource(dev, FIRMWARE_PCI_REG_BASE,<br>                           FIRMWARE_PHYS_BASE >> 10,<br>                               FIRMWARE_PHYS_LENGTH >> 10);<br></pre><p>To view, visit <a href="https://review.coreboot.org/21103">change 21103</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/21103"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Iaa68319da5fb999fe8d73792eaee692cce60c8a2 </div>
<div style="display:none"> Gerrit-Change-Number: 21103 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Matt DeVillier <matt.devillier@gmail.com> </div>