[coreboot-gerrit] Change in coreboot[master]: common/block/fast_spi: Add function to DLOCK PR registers

[Barnali Sarkar (Code Review)]

Barnali Sarkar has uploaded this change for review. ( https://review.coreboot.org/21063


Change subject: common/block/fast_spi: Add function to DLOCK PR registers
......................................................................

common/block/fast_spi: Add function to DLOCK PR registers

Add a function in FAST_SPI library to discrete lock the PR
registers 0 to 4.

BUG=none
BRANCH=none
TEST=Build and boot poppy

Change-Id: I46e1948315ea9489932efdf7d60d6d78ab3948a6
Signed-off-by: Barnali Sarkar <barnali.sarkar at intel.com>
---
M src/soc/intel/common/block/fast_spi/fast_spi.c
M src/soc/intel/common/block/fast_spi/fast_spi_def.h
M src/soc/intel/common/block/include/intelblocks/fast_spi.h
3 files changed, 30 insertions(+), 0 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/21063/1

diff --git a/src/soc/intel/common/block/fast_spi/fast_spi.c b/src/soc/intel/common/block/fast_spi/fast_spi.c
index fe0217a..dbb25d7 100644
--- a/src/soc/intel/common/block/fast_spi/fast_spi.c
+++ b/src/soc/intel/common/block/fast_spi/fast_spi.c
@@ -149,6 +149,23 @@
 	write16(spibar + SPIBAR_HSFSTS_CTL, hsfs);
 }
 
+/*.
+ * Set FAST_SPIBAR + DLOCK (0x0C) register bits to discrete lock the
+ * FAST_SPI Protected Range (PR) registers.
+ */
+void fast_spi_pr_dlock(void)
+{
+	void *spibar = fast_spi_get_bar();
+	uint32_t dlock;
+
+	dlock = read32(spibar + SPIBAR_DLOCK);
+	dlock |= (SPIBAR_DLOCK_PR0LOCKDN | SPIBAR_DLOCK_PR1LOCKDN
+			| SPIBAR_DLOCK_PR2LOCKDN | SPIBAR_DLOCK_PR3LOCKDN
+			| SPIBAR_DLOCK_PR4LOCKDN);
+
+	write32(spibar + SPIBAR_DLOCK, dlock);
+}
+
 /*
  * Set FAST_SPIBAR Soft Reset Data Register value.
  */
diff --git a/src/soc/intel/common/block/fast_spi/fast_spi_def.h b/src/soc/intel/common/block/fast_spi/fast_spi_def.h
index 8e06df2..5b83265 100644
--- a/src/soc/intel/common/block/fast_spi/fast_spi_def.h
+++ b/src/soc/intel/common/block/fast_spi/fast_spi_def.h
@@ -34,6 +34,7 @@
 #define SPIBAR_BFPREG			0x00
 #define SPIBAR_HSFSTS_CTL		0x04
 #define SPIBAR_FADDR			0x08
+#define SPIBAR_DLOCK		0x0c
 #define SPIBAR_FDATA(n)			(0x10 + ((n) & 0xf) * 4)
 #define SPIBAR_FPR_BASE			0x84
 #define SPIBAR_FPR(n)			0x84 + (4 * n))
@@ -87,6 +88,13 @@
 /* Bit definitions for FADDR (0x08) register */
 #define SPIBAR_FADDR_MASK		0x7FFFFFF
 
+/* Bit definitions for DLOCK (0x0C) register */
+#define SPIBAR_DLOCK_PR0LOCKDN		(1 << 8)
+#define SPIBAR_DLOCK_PR1LOCKDN		(1 << 9)
+#define SPIBAR_DLOCK_PR2LOCKDN		(1 << 10)
+#define SPIBAR_DLOCK_PR3LOCKDN		(1 << 11)
+#define SPIBAR_DLOCK_PR4LOCKDN		(1 << 12)
+
 /* Maximum bytes of data that can fit in FDATAn (0x10) registers */
 #define SPIBAR_FDATA_FIFO_SIZE		0x40
 
diff --git a/src/soc/intel/common/block/include/intelblocks/fast_spi.h b/src/soc/intel/common/block/include/intelblocks/fast_spi.h
index b399e4d..e93c546 100644
--- a/src/soc/intel/common/block/include/intelblocks/fast_spi.h
+++ b/src/soc/intel/common/block/include/intelblocks/fast_spi.h
@@ -48,6 +48,11 @@
  * Lock FAST_SPIBAR.
  */
 void fast_spi_lock_bar(void);
+/*.
+ * Set FAST_SPIBAR + DLOCK (0x0C) register bits to discrete lock the
+ * FAST_SPI Protected Range (PR) registers.
+ */
+void fast_spi_pr_dlock(void);
 /*
  * Set FAST_SPIBAR Soft Reset Data Register value.
  */

-- 
To view, visit https://review.coreboot.org/21063
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I46e1948315ea9489932efdf7d60d6d78ab3948a6
Gerrit-Change-Number: 21063
Gerrit-PatchSet: 1
Gerrit-Owner: Barnali Sarkar <barnali.sarkar at intel.com>
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