<p>Barnali Sarkar has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/21063">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">common/block/fast_spi: Add function to DLOCK PR registers<br><br>Add a function in FAST_SPI library to discrete lock the PR<br>registers 0 to 4.<br><br>BUG=none<br>BRANCH=none<br>TEST=Build and boot poppy<br><br>Change-Id: I46e1948315ea9489932efdf7d60d6d78ab3948a6<br>Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com><br>---<br>M src/soc/intel/common/block/fast_spi/fast_spi.c<br>M src/soc/intel/common/block/fast_spi/fast_spi_def.h<br>M src/soc/intel/common/block/include/intelblocks/fast_spi.h<br>3 files changed, 30 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/21063/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/soc/intel/common/block/fast_spi/fast_spi.c b/src/soc/intel/common/block/fast_spi/fast_spi.c<br>index fe0217a..dbb25d7 100644<br>--- a/src/soc/intel/common/block/fast_spi/fast_spi.c<br>+++ b/src/soc/intel/common/block/fast_spi/fast_spi.c<br>@@ -149,6 +149,23 @@<br>        write16(spibar + SPIBAR_HSFSTS_CTL, hsfs);<br> }<br> <br>+/*.<br>+ * Set FAST_SPIBAR + DLOCK (0x0C) register bits to discrete lock the<br>+ * FAST_SPI Protected Range (PR) registers.<br>+ */<br>+void fast_spi_pr_dlock(void)<br>+{<br>+        void *spibar = fast_spi_get_bar();<br>+   uint32_t dlock;<br>+<br>+   dlock = read32(spibar + SPIBAR_DLOCK);<br>+       dlock |= (SPIBAR_DLOCK_PR0LOCKDN | SPIBAR_DLOCK_PR1LOCKDN<br>+                    | SPIBAR_DLOCK_PR2LOCKDN | SPIBAR_DLOCK_PR3LOCKDN<br>+                    | SPIBAR_DLOCK_PR4LOCKDN);<br>+<br>+        write32(spibar + SPIBAR_DLOCK, dlock);<br>+}<br>+<br> /*<br>  * Set FAST_SPIBAR Soft Reset Data Register value.<br>  */<br>diff --git a/src/soc/intel/common/block/fast_spi/fast_spi_def.h b/src/soc/intel/common/block/fast_spi/fast_spi_def.h<br>index 8e06df2..5b83265 100644<br>--- a/src/soc/intel/common/block/fast_spi/fast_spi_def.h<br>+++ b/src/soc/intel/common/block/fast_spi/fast_spi_def.h<br>@@ -34,6 +34,7 @@<br> #define SPIBAR_BFPREG                       0x00<br> #define SPIBAR_HSFSTS_CTL                0x04<br> #define SPIBAR_FADDR                     0x08<br>+#define SPIBAR_DLOCK             0x0c<br> #define SPIBAR_FDATA(n)                  (0x10 + ((n) & 0xf) * 4)<br> #define SPIBAR_FPR_BASE                  0x84<br> #define SPIBAR_FPR(n)                    0x84 + (4 * n))<br>@@ -87,6 +88,13 @@<br> /* Bit definitions for FADDR (0x08) register */<br> #define SPIBAR_FADDR_MASK               0x7FFFFFF<br> <br>+/* Bit definitions for DLOCK (0x0C) register */<br>+#define SPIBAR_DLOCK_PR0LOCKDN         (1 << 8)<br>+#define SPIBAR_DLOCK_PR1LOCKDN         (1 << 9)<br>+#define SPIBAR_DLOCK_PR2LOCKDN         (1 << 10)<br>+#define SPIBAR_DLOCK_PR3LOCKDN                (1 << 11)<br>+#define SPIBAR_DLOCK_PR4LOCKDN                (1 << 12)<br>+<br> /* Maximum bytes of data that can fit in FDATAn (0x10) registers */<br> #define SPIBAR_FDATA_FIFO_SIZE               0x40<br> <br>diff --git a/src/soc/intel/common/block/include/intelblocks/fast_spi.h b/src/soc/intel/common/block/include/intelblocks/fast_spi.h<br>index b399e4d..e93c546 100644<br>--- a/src/soc/intel/common/block/include/intelblocks/fast_spi.h<br>+++ b/src/soc/intel/common/block/include/intelblocks/fast_spi.h<br>@@ -48,6 +48,11 @@<br>  * Lock FAST_SPIBAR.<br>  */<br> void fast_spi_lock_bar(void);<br>+/*.<br>+ * Set FAST_SPIBAR + DLOCK (0x0C) register bits to discrete lock the<br>+ * FAST_SPI Protected Range (PR) registers.<br>+ */<br>+void fast_spi_pr_dlock(void);<br> /*<br>  * Set FAST_SPIBAR Soft Reset Data Register value.<br>  */<br></pre><p>To view, visit <a href="https://review.coreboot.org/21063">change 21063</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/21063"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I46e1948315ea9489932efdf7d60d6d78ab3948a6 </div>
<div style="display:none"> Gerrit-Change-Number: 21063 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Barnali Sarkar <barnali.sarkar@intel.com> </div>