[coreboot-gerrit] Change in coreboot[master]: amd/padmelon: Fixes to enable power button
John E. Kabat (Code Review)
gerrit at coreboot.org
Wed Aug 16 16:28:26 CEST 2017
John E. Kabat has uploaded this change for review. ( https://review.coreboot.org/21048
Change subject: amd/padmelon: Fixes to enable power button
......................................................................
amd/padmelon: Fixes to enable power button
More fixes to enable the power button, remove uneeded code
and general cleanup
In gpe.asl clear the PSIN_FLAG in the sio.
In dsdt.asl use the superio.asl file in the f81803a directory.
The remainder is general cleanup due to changes in amd code.
Change-Id: I104a6d3cabc15f0a61d6197d6aeb5189ce2e483b
---
M src/mainboard/amd/padmelon/BiosCallOuts.c
M src/mainboard/amd/padmelon/Kconfig
M src/mainboard/amd/padmelon/OemCustomize.c
M src/mainboard/amd/padmelon/acpi/gpe.asl
M src/mainboard/amd/padmelon/devicetree.cb
M src/mainboard/amd/padmelon/dsdt.asl
M src/mainboard/amd/padmelon/romstage.c
7 files changed, 31 insertions(+), 36 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/21048/1
diff --git a/src/mainboard/amd/padmelon/BiosCallOuts.c b/src/mainboard/amd/padmelon/BiosCallOuts.c
index 91c5efe..1c19912 100644
--- a/src/mainboard/amd/padmelon/BiosCallOuts.c
+++ b/src/mainboard/amd/padmelon/BiosCallOuts.c
@@ -15,29 +15,23 @@
#include <device/pci_def.h>
#include <device/device.h>
-#include "AGESA.h"
-#include "amdlib.h"
-#include <northbridge/amd/pi/BiosCallOuts.h>
+#include <AGESA.h>
+#include <amdlib.h>
+#include <northbridge/amd/agesa/BiosCallOuts.h>
#include <northbridge/amd/pi/00660F01/chip.h>
-#include "Ids.h"
-#include "heapManager.h"
-#include "FchPlatform.h"
-#include "cbfs.h"
-#include "imc.h"
-#include "hudson.h"
+#include <Ids.h>
+#include <heapManager.h>
+#include <FchPlatform.h>
+#include <cbfs.h>
+#include <imc.h>
+#include <hudson.h>
#include <stdlib.h>
-#include "BiosCallOuts.h"
#include "northbridge/amd/pi/dimmSpd.h"
#include "northbridge/amd/pi/agesawrapper.h"
-#include <boardid.h>
static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINTN FchData, VOID *ConfigPtr);
-const BIOS_CALLOUT_STRUCT BiosCallouts[] =
-{
- {AGESA_ALLOCATE_BUFFER, agesa_AllocateBuffer },
- {AGESA_DEALLOCATE_BUFFER, agesa_DeallocateBuffer },
- {AGESA_LOCATE_BUFFER, agesa_LocateBuffer },
+const BIOS_CALLOUT_STRUCT BiosCallouts[] = {
{AGESA_READ_SPD, agesa_ReadSpd },
{AGESA_DO_RESET, agesa_Reset },
{AGESA_READ_SPD_RECOVERY, agesa_NoopUnsupported },
@@ -70,6 +64,7 @@
FchParams_reset->FchReset.SataEnable = hudson_sata_enable();
FchParams_reset->FchReset.IdeEnable = hudson_ide_enable();
FchParams_reset->FchReset.Xhci0Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE);
+ FchParams_reset->FchReset.Xhci1Enable = FALSE;
FchParams_reset->EarlyOemGpioTable = oem_padmelon_gpio;
} else if (StdHeader->Func == AMD_INIT_ENV) {
FCH_DATA_BLOCK *FchParams_env = (FCH_DATA_BLOCK *)FchData;
@@ -82,8 +77,8 @@
FchParams_env->Usb.Xhci0Enable = TRUE;
else
FchParams_env->Usb.Xhci0Enable = FALSE;
+ FchParams_env->Usb.Xhci1Enable = FALSE;
FchParams_env->Usb.USB30PortInit = 8; /* 8: If USB3 port is unremoveable. */
-
/* SD configuration */
FchParams_env->Sd.SdSlotType = 1; /* eMMC */
}
diff --git a/src/mainboard/amd/padmelon/Kconfig b/src/mainboard/amd/padmelon/Kconfig
index 7f75dc4..b518149 100644
--- a/src/mainboard/amd/padmelon/Kconfig
+++ b/src/mainboard/amd/padmelon/Kconfig
@@ -17,6 +17,7 @@
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
+ select BINARYPI_LEGACY_WRAPPER
select CPU_AMD_PI_00660F01
select NORTHBRIDGE_AMD_PI_00660F01
select SOUTHBRIDGE_AMD_PI_KERN
diff --git a/src/mainboard/amd/padmelon/OemCustomize.c b/src/mainboard/amd/padmelon/OemCustomize.c
index 9ed7e42..2516fde 100644
--- a/src/mainboard/amd/padmelon/OemCustomize.c
+++ b/src/mainboard/amd/padmelon/OemCustomize.c
@@ -13,9 +13,9 @@
* GNU General Public License for more details.
*/
-#include <northbridge/amd/pi/agesawrapper.h>
+#include <northbridge/amd/agesa/agesawrapper.h>
#include <PlatformMemoryConfiguration.h>
-#include <boardid.h>
+#include <vendorcode/amd/pi/00660F01/AGESA.h>
#define FILECODE PROC_GNB_PCIE_FAMILY_0X15_F15PCIECOMPLEXCONFIG_FILECODE
diff --git a/src/mainboard/amd/padmelon/acpi/gpe.asl b/src/mainboard/amd/padmelon/acpi/gpe.asl
index ba8d878..095d3c1 100644
--- a/src/mainboard/amd/padmelon/acpi/gpe.asl
+++ b/src/mainboard/amd/padmelon/acpi/gpe.asl
@@ -17,11 +17,11 @@
/* General event 3 */
Method(_L03) {
- /* DBGO("\\_GPE\\_L03\n") */
- Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
+ /* DBGO("\\_GPE\\_L03\n") */
+ Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
}
- /* Legacy PM event - Power Button */
+ /* Legacy PM event - Power Button */
Method(_L08) {
/* DBGO("\\_GPE\\_L08\n") */
\_SB.SIO0.CPSI() /* clear psin state in sio */
@@ -77,4 +77,4 @@
Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */
Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
}
-} /* End Scope GPE */
+} /* End Scope GPE */
diff --git a/src/mainboard/amd/padmelon/devicetree.cb b/src/mainboard/amd/padmelon/devicetree.cb
index f47cc70..82b57b3 100644
--- a/src/mainboard/amd/padmelon/devicetree.cb
+++ b/src/mainboard/amd/padmelon/devicetree.cb
@@ -25,7 +25,7 @@
chip northbridge/amd/pi/00660F01 # PCI side of HT root complex
device pci 0.0 on end # Root Complex
- device pci 1.0 on end # Internal Graphics P2P bridge 0x9804
+ device pci 1.0 on end # Internal Graphics P2P bridge 0x9874
device pci 1.1 on end # Internal Multimedia
device pci 2.0 on end # PCIe Host Bridge
device pci 2.1 off end # No x4 PCIe slot
@@ -54,6 +54,7 @@
end # SM
device pci 14.3 on # LPC 0x439d
chip superio/fintek/f81803a
+ register "conf_key_mode" = "0x77"
device pnp 4e.1 on # COM1
io 0x60 = 0x3f8
irq 0x70 = 4
@@ -67,7 +68,6 @@
device pnp 4e.6 off end # GPIO
device pnp 4e.7 off end # WDT
device pnp 4e.a on end # PME
-
end # f81803a
end # LPC
device pci 14.7 on end # SD
diff --git a/src/mainboard/amd/padmelon/dsdt.asl b/src/mainboard/amd/padmelon/dsdt.asl
index 470ee26..76adaa4 100644
--- a/src/mainboard/amd/padmelon/dsdt.asl
+++ b/src/mainboard/amd/padmelon/dsdt.asl
@@ -72,8 +72,8 @@
/* Describe the devices in the Southbridge */
#include "acpi/carrizo_fch.asl"
- /* Describe the Fintek F81803A SIO */
- #include "acpi/superio.asl"
+ /* Describe the Fintek F81803A SIO */
+ #include <superio/fintek/f81803a/acpi/superio.asl>
} /* End \_SB scope */
diff --git a/src/mainboard/amd/padmelon/romstage.c b/src/mainboard/amd/padmelon/romstage.c
index 7f29002..f53d66f 100644
--- a/src/mainboard/amd/padmelon/romstage.c
+++ b/src/mainboard/amd/padmelon/romstage.c
@@ -20,6 +20,7 @@
#include <cpu/x86/lapic.h>
#include <cpu/x86/bist.h>
#include <cpu/amd/car.h>
+#include <northbridge/amd/agesa/state_machine.h>
#include <northbridge/amd/pi/agesawrapper.h>
#include <northbridge/amd/pi/agesawrapper_call.h>
#include <southbridge/amd/pi/hudson/hudson.h>
@@ -32,9 +33,6 @@
{
u32 val;
- /* Must come first to enable PCI MMCONF. */
- amd_initmmio();
-
hudson_lpc_port80();
if (!cpu_init_detectedx && boot_cpu()) {
@@ -42,6 +40,9 @@
hudson_clk_output_48Mhz(2);
fintek_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+#if IS_ENABLED(CONFIG_HUDSON_UART)
+ configure_hudson_uart();
+#endif
post_code(0x31);
console_init();
}
@@ -65,18 +66,16 @@
post_code(0x40);
AGESAWRAPPER(amdinitpost);
+}
+
+void agesa_postcar(struct sysinfo *cb)
+{
post_code(0x41);
AGESAWRAPPER(amdinitenv);
- /* TODO: Disable cache is not ok. */
- disable_cache_as_ram();
if (acpi_is_wakeup_s4()) {
outb(0xEE, PM_INDEX);
outb(0x8, PM_DATA);
}
- post_code(0x50);
- copy_and_run();
-
- post_code(0x54); /* Should never see this post code. */
}
--
To view, visit https://review.coreboot.org/21048
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I104a6d3cabc15f0a61d6197d6aeb5189ce2e483b
Gerrit-Change-Number: 21048
Gerrit-PatchSet: 1
Gerrit-Owner: John E. Kabat <sljkrr at gmail.com>
Gerrit-Reviewer: John E. Kabat Jr. <john.kabat at scarletltd.com>
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