<p>John E. Kabat has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/21048">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">amd/padmelon: Fixes to enable power button<br><br>More fixes to enable the power button, remove uneeded code<br>and general cleanup<br>In gpe.asl clear the PSIN_FLAG in the sio.<br>In dsdt.asl use the superio.asl file in the f81803a directory.<br>The remainder is general cleanup due to changes in amd code.<br><br>Change-Id: I104a6d3cabc15f0a61d6197d6aeb5189ce2e483b<br>---<br>M src/mainboard/amd/padmelon/BiosCallOuts.c<br>M src/mainboard/amd/padmelon/Kconfig<br>M src/mainboard/amd/padmelon/OemCustomize.c<br>M src/mainboard/amd/padmelon/acpi/gpe.asl<br>M src/mainboard/amd/padmelon/devicetree.cb<br>M src/mainboard/amd/padmelon/dsdt.asl<br>M src/mainboard/amd/padmelon/romstage.c<br>7 files changed, 31 insertions(+), 36 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/21048/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/mainboard/amd/padmelon/BiosCallOuts.c b/src/mainboard/amd/padmelon/BiosCallOuts.c<br>index 91c5efe..1c19912 100644<br>--- a/src/mainboard/amd/padmelon/BiosCallOuts.c<br>+++ b/src/mainboard/amd/padmelon/BiosCallOuts.c<br>@@ -15,29 +15,23 @@<br> <br> #include <device/pci_def.h><br> #include <device/device.h><br>-#include "AGESA.h"<br>-#include "amdlib.h"<br>-#include <northbridge/amd/pi/BiosCallOuts.h><br>+#include <AGESA.h><br>+#include <amdlib.h><br>+#include <northbridge/amd/agesa/BiosCallOuts.h><br> #include <northbridge/amd/pi/00660F01/chip.h><br>-#include "Ids.h"<br>-#include "heapManager.h"<br>-#include "FchPlatform.h"<br>-#include "cbfs.h"<br>-#include "imc.h"<br>-#include "hudson.h"<br>+#include <Ids.h><br>+#include <heapManager.h><br>+#include <FchPlatform.h><br>+#include <cbfs.h><br>+#include <imc.h><br>+#include <hudson.h><br> #include <stdlib.h><br>-#include "BiosCallOuts.h"<br> #include "northbridge/amd/pi/dimmSpd.h"<br> #include "northbridge/amd/pi/agesawrapper.h"<br>-#include <boardid.h><br> <br> static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINTN FchData, VOID *ConfigPtr);<br> <br>-const BIOS_CALLOUT_STRUCT BiosCallouts[] =<br>-{<br>- {AGESA_ALLOCATE_BUFFER, agesa_AllocateBuffer },<br>- {AGESA_DEALLOCATE_BUFFER, agesa_DeallocateBuffer },<br>- {AGESA_LOCATE_BUFFER, agesa_LocateBuffer },<br>+const BIOS_CALLOUT_STRUCT BiosCallouts[] = {<br> {AGESA_READ_SPD, agesa_ReadSpd },<br> {AGESA_DO_RESET, agesa_Reset },<br> {AGESA_READ_SPD_RECOVERY, agesa_NoopUnsupported },<br>@@ -70,6 +64,7 @@<br> FchParams_reset->FchReset.SataEnable = hudson_sata_enable();<br> FchParams_reset->FchReset.IdeEnable = hudson_ide_enable();<br> FchParams_reset->FchReset.Xhci0Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE);<br>+ FchParams_reset->FchReset.Xhci1Enable = FALSE;<br> FchParams_reset->EarlyOemGpioTable = oem_padmelon_gpio;<br> } else if (StdHeader->Func == AMD_INIT_ENV) {<br> FCH_DATA_BLOCK *FchParams_env = (FCH_DATA_BLOCK *)FchData;<br>@@ -82,8 +77,8 @@<br> FchParams_env->Usb.Xhci0Enable = TRUE;<br> else<br> FchParams_env->Usb.Xhci0Enable = FALSE;<br>+ FchParams_env->Usb.Xhci1Enable = FALSE;<br> FchParams_env->Usb.USB30PortInit = 8; /* 8: If USB3 port is unremoveable. */<br>-<br> /* SD configuration */<br> FchParams_env->Sd.SdSlotType = 1; /* eMMC */<br> }<br>diff --git a/src/mainboard/amd/padmelon/Kconfig b/src/mainboard/amd/padmelon/Kconfig<br>index 7f75dc4..b518149 100644<br>--- a/src/mainboard/amd/padmelon/Kconfig<br>+++ b/src/mainboard/amd/padmelon/Kconfig<br>@@ -17,6 +17,7 @@<br> <br> config BOARD_SPECIFIC_OPTIONS # dummy<br> def_bool y<br>+ select BINARYPI_LEGACY_WRAPPER<br> select CPU_AMD_PI_00660F01<br> select NORTHBRIDGE_AMD_PI_00660F01<br> select SOUTHBRIDGE_AMD_PI_KERN<br>diff --git a/src/mainboard/amd/padmelon/OemCustomize.c b/src/mainboard/amd/padmelon/OemCustomize.c<br>index 9ed7e42..2516fde 100644<br>--- a/src/mainboard/amd/padmelon/OemCustomize.c<br>+++ b/src/mainboard/amd/padmelon/OemCustomize.c<br>@@ -13,9 +13,9 @@<br> * GNU General Public License for more details.<br> */<br> <br>-#include <northbridge/amd/pi/agesawrapper.h><br>+#include <northbridge/amd/agesa/agesawrapper.h><br> #include <PlatformMemoryConfiguration.h><br>-#include <boardid.h><br>+#include <vendorcode/amd/pi/00660F01/AGESA.h><br> <br> #define FILECODE PROC_GNB_PCIE_FAMILY_0X15_F15PCIECOMPLEXCONFIG_FILECODE<br> <br>diff --git a/src/mainboard/amd/padmelon/acpi/gpe.asl b/src/mainboard/amd/padmelon/acpi/gpe.asl<br>index ba8d878..095d3c1 100644<br>--- a/src/mainboard/amd/padmelon/acpi/gpe.asl<br>+++ b/src/mainboard/amd/padmelon/acpi/gpe.asl<br>@@ -17,11 +17,11 @@<br> <br> /* General event 3 */<br> Method(_L03) {<br>- /* DBGO("\\_GPE\\_L03\n") */<br>- Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */<br>+ /* DBGO("\\_GPE\\_L03\n") */<br>+ Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */<br> }<br> <br>- /* Legacy PM event - Power Button */<br>+ /* Legacy PM event - Power Button */<br> Method(_L08) {<br> /* DBGO("\\_GPE\\_L08\n") */<br> \_SB.SIO0.CPSI() /* clear psin state in sio */<br>@@ -77,4 +77,4 @@<br> Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */<br> Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */<br> }<br>-} /* End Scope GPE */<br>+} /* End Scope GPE */<br>diff --git a/src/mainboard/amd/padmelon/devicetree.cb b/src/mainboard/amd/padmelon/devicetree.cb<br>index f47cc70..82b57b3 100644<br>--- a/src/mainboard/amd/padmelon/devicetree.cb<br>+++ b/src/mainboard/amd/padmelon/devicetree.cb<br>@@ -25,7 +25,7 @@<br> <br> chip northbridge/amd/pi/00660F01 # PCI side of HT root complex<br> device pci 0.0 on end # Root Complex<br>- device pci 1.0 on end # Internal Graphics P2P bridge 0x9804<br>+ device pci 1.0 on end # Internal Graphics P2P bridge 0x9874<br> device pci 1.1 on end # Internal Multimedia<br> device pci 2.0 on end # PCIe Host Bridge<br> device pci 2.1 off end # No x4 PCIe slot<br>@@ -54,6 +54,7 @@<br> end # SM<br> device pci 14.3 on # LPC 0x439d<br> chip superio/fintek/f81803a<br>+ register "conf_key_mode" = "0x77"<br> device pnp 4e.1 on # COM1<br> io 0x60 = 0x3f8<br> irq 0x70 = 4<br>@@ -67,7 +68,6 @@<br> device pnp 4e.6 off end # GPIO<br> device pnp 4e.7 off end # WDT<br> device pnp 4e.a on end # PME<br>- <br> end # f81803a<br> end # LPC<br> device pci 14.7 on end # SD<br>diff --git a/src/mainboard/amd/padmelon/dsdt.asl b/src/mainboard/amd/padmelon/dsdt.asl<br>index 470ee26..76adaa4 100644<br>--- a/src/mainboard/amd/padmelon/dsdt.asl<br>+++ b/src/mainboard/amd/padmelon/dsdt.asl<br>@@ -72,8 +72,8 @@<br> /* Describe the devices in the Southbridge */<br> #include "acpi/carrizo_fch.asl"<br> <br>- /* Describe the Fintek F81803A SIO */<br>- #include "acpi/superio.asl"<br>+ /* Describe the Fintek F81803A SIO */<br>+ #include <superio/fintek/f81803a/acpi/superio.asl><br> <br> } /* End \_SB scope */<br> <br>diff --git a/src/mainboard/amd/padmelon/romstage.c b/src/mainboard/amd/padmelon/romstage.c<br>index 7f29002..f53d66f 100644<br>--- a/src/mainboard/amd/padmelon/romstage.c<br>+++ b/src/mainboard/amd/padmelon/romstage.c<br>@@ -20,6 +20,7 @@<br> #include <cpu/x86/lapic.h><br> #include <cpu/x86/bist.h><br> #include <cpu/amd/car.h><br>+#include <northbridge/amd/agesa/state_machine.h><br> #include <northbridge/amd/pi/agesawrapper.h><br> #include <northbridge/amd/pi/agesawrapper_call.h><br> #include <southbridge/amd/pi/hudson/hudson.h><br>@@ -32,9 +33,6 @@<br> {<br> u32 val;<br> <br>- /* Must come first to enable PCI MMCONF. */<br>- amd_initmmio();<br>-<br> hudson_lpc_port80();<br> <br> if (!cpu_init_detectedx && boot_cpu()) {<br>@@ -42,6 +40,9 @@<br> hudson_clk_output_48Mhz(2);<br> fintek_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);<br> <br>+#if IS_ENABLED(CONFIG_HUDSON_UART)<br>+ configure_hudson_uart();<br>+#endif<br> post_code(0x31);<br> console_init();<br> }<br>@@ -65,18 +66,16 @@<br> <br> post_code(0x40);<br> AGESAWRAPPER(amdinitpost);<br>+}<br>+<br>+void agesa_postcar(struct sysinfo *cb)<br>+{<br> post_code(0x41);<br> AGESAWRAPPER(amdinitenv);<br>- /* TODO: Disable cache is not ok. */<br>- disable_cache_as_ram();<br> <br> if (acpi_is_wakeup_s4()) {<br> outb(0xEE, PM_INDEX);<br> outb(0x8, PM_DATA);<br> }<br> <br>- post_code(0x50);<br>- copy_and_run();<br>-<br>- post_code(0x54); /* Should never see this post code. */<br> }<br></pre><p>To view, visit <a href="https://review.coreboot.org/21048">change 21048</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/21048"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I104a6d3cabc15f0a61d6197d6aeb5189ce2e483b </div>
<div style="display:none"> Gerrit-Change-Number: 21048 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: John E. Kabat <sljkrr@gmail.com> </div>
<div style="display:none"> Gerrit-Reviewer: John E. Kabat Jr. <john.kabat@scarletltd.com> </div>