[coreboot-gerrit] Change in coreboot[master]: amd/padmelon: Adding more Fintek F81803A files
John E. Kabat (Code Review)
gerrit at coreboot.org
Wed Aug 16 16:28:21 CEST 2017
Hello John E. Kabat Jr.,
I'd like you to do a code review. Please visit
https://review.coreboot.org/21047
to review the following change.
Change subject: amd/padmelon: Adding more Fintek F81803A files
......................................................................
amd/padmelon: Adding more Fintek F81803A files
This reorganizes the Fintek F81803A files and adds new features.
superio.asl add access to PME ACPI Control Register 5 for clearing
the PSIN_FLAG. Method CPSI() is used by asl power button code to clear this.
f81803a.h consolidates all the bit and register definition in one place.
superio.c consolidates all the initialization functions.
Superio.asl moved to the acpi directory.
chip.h fintek_internal.h and f81803a_pme.c have been folded into other
files and are no longer needed
Change-Id: Ib4b078a590ba27f698dad84d6bd6237c8331e60f
Signed-off-by: John Kabat <john.kabat at scarletltd.com>
---
M src/superio/fintek/f81803a/Makefile.inc
A src/superio/fintek/f81803a/acpi/superio.asl
D src/superio/fintek/f81803a/chip.h
M src/superio/fintek/f81803a/f81803a.h
D src/superio/fintek/f81803a/f81803a_pme.c
D src/superio/fintek/f81803a/fintek_internal.h
M src/superio/fintek/f81803a/superio.c
7 files changed, 217 insertions(+), 239 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/21047/1
diff --git a/src/superio/fintek/f81803a/Makefile.inc b/src/superio/fintek/f81803a/Makefile.inc
index 372de05..9156bf9 100644
--- a/src/superio/fintek/f81803a/Makefile.inc
+++ b/src/superio/fintek/f81803a/Makefile.inc
@@ -15,4 +15,3 @@
##
ramstage-$(CONFIG_SUPERIO_FINTEK_F81803A) += superio.c
-ramstage-$(CONFIG_SUPERIO_FINTEK_F81803A) += f81803a_pme.c
diff --git a/src/superio/fintek/f81803a/acpi/superio.asl b/src/superio/fintek/f81803a/acpi/superio.asl
new file mode 100644
index 0000000..7568131
--- /dev/null
+++ b/src/superio/fintek/f81803a/acpi/superio.asl
@@ -0,0 +1,155 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Christoph Grenz <christophg+cb at grenz-bonn.de>
+ * Copyright (C) 2013 secunet Security Networks AG
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/*
+ * Include this file into a mainboard's DSDT _SB device tree and it will
+ * expose the F81803A SuperIO and some of its functionality.
+ *
+ * It allows the change of IO ports, IRQs and DMA settings on logical
+ * devices, disabling and reenabling logical devices and controlling power
+ * saving mode on logical devices or the whole chip.
+ *
+ * LDN State
+ * 0x1 UARTA Implemented, partially tested
+ * 0x2 UARTB UART only, partially tested
+ * 0x4 HWM Not implemented
+ * 0x5 KBC Implemented, untested
+ * 0x6 GPIO6 Not implemented
+ * 0x7 WDT0&PLED Not implemented
+ * 0xa ACPI/PME/ERP Partially implemented
+ *
+ * Controllable through preprocessor defines:
+ * SUPERIO_DEV Device identifier for this SIO (e.g. SIO0)
+ * SUPERIO_PNP_BASE I/o address of the first PnP configuration register
+ * F81803A_SHOW_UARTA If defined, UARTA will be exposed.
+ * F81803A_SHOW_UARTB If defined, UARTB will be exposed.
+ * F81803A_SHOW_KBC If defined, the KBC will be exposed.
+ * F81803A_SHOW_PS2M If defined, PS/2 mouse support will be exposed.
+ * F81803A_SHOW_HWMON If defined, the hardware monitor will be exposed.
+ * F81803A_SHOW_PME If defined, the PME/EARP/ACPI will be exposed.
+ */
+#undef SUPERIO_DEV
+#define SUPERIO_DEV SIO0
+#undef SUPERIO_CHIP_NAME
+#define SUPERIO_CHIP_NAME F81803A
+#define SUPERIO_PNP_BASE 0x4E
+#define F81803A_SHOW_PME
+#include <superio/acpi/pnp.asl>
+
+
+
+Device(SUPERIO_DEV) {
+ Name (_HID, EisaId("PNP0A05"))
+ Name (_STR, Unicode("Fintek F81803A Super I/O"))
+ Name (_UID, SUPERIO_UID(SUPERIO_DEV,))
+
+ /* Mutex for accesses to the configuration ports */
+ Mutex(CRMX, 1)
+
+ /* SuperIO configuration ports */
+ OperationRegion (CREG, SystemIO, SUPERIO_PNP_BASE, 0x02)
+ Field (CREG, ByteAcc, NoLock, Preserve)
+ {
+ PNP_ADDR_REG, 8,
+ PNP_DATA_REG, 8
+ }
+ IndexField (ADDR, DATA, ByteAcc, NoLock, Preserve)
+ {
+ Offset (0x07),
+ PNP_LOGICAL_DEVICE, 8, /* Logical device selector */
+ Offset (0x30),
+ PNP_DEVICE_ACTIVE, 1, /* Logical device activation */
+ Offset (0x60),
+ PNP_IO0_HIGH_BYTE, 8, /* First I/O port base - high byte */
+ PNP_IO0_LOW_BYTE, 8, /* First I/O port base - low byte */
+ Offset (0x62),
+ PNP_IO1_HIGH_BYTE, 8, /* Second I/O port base - high byte */
+ PNP_IO1_LOW_BYTE, 8, /* Second I/O port base - low byte */
+ Offset (0x70),
+ PNP_IRQ0, 8, /* First IRQ */
+ offset(0xFB),
+ APC5, 8, /* PME ACPI Control Register 5 */
+ }
+
+ Method(_CRS)
+ {
+ /* Announce the used i/o ports to the OS */
+ Return (ResourceTemplate () {
+ IO (Decode16, SUPERIO_PNP_BASE, SUPERIO_PNP_BASE, 0x01, 0x02)
+ })
+ }
+
+ #undef PNP_ENTER_MAGIC_1ST
+ #undef PNP_ENTER_MAGIC_2ND
+ #undef PNP_ENTER_MAGIC_3RD
+ #undef PNP_ENTER_MAGIC_4TH
+ #undef PNP_EXIT_MAGIC_1ST
+ #undef PNP_EXIT_SPECIAL_REG
+ #undef PNP_EXIT_SPECIAL_VAL
+ #define PNP_ENTER_MAGIC_1ST 0x87
+ #define PNP_ENTER_MAGIC_2ND 0x87
+ #define PNP_EXIT_MAGIC_1ST 0xaa
+ #include <superio/acpi/pnp_config.asl>
+
+#ifdef F81803A_SHOW_UARTA
+ #undef SUPERIO_UART_LDN
+ #undef SUPERIO_UART_DDN
+ #undef SUPERIO_UART_PM_REG
+ #undef SUPERIO_UART_PM_VAL
+ #undef SUPERIO_UART_PM_LDN
+ #define SUPERIO_UART_LDN 1
+ #define SUPERIO_UART_PM_REG UAPW
+ #define SUPERIO_UART_PM_VAL 0
+ #define SUPERIO_UART_PM_LDN PNP_NO_LDN_CHANGE
+ #include <superio/acpi/pnp_uart.asl>
+#endif
+
+#ifdef F81803A_SHOW_UARTB
+ #undef SUPERIO_UART_LDN
+ #undef SUPERIO_UART_DDN
+ #undef SUPERIO_UART_PM_REG
+ #undef SUPERIO_UART_PM_VAL
+ #undef SUPERIO_UART_PM_LDN
+ #define SUPERIO_UART_LDN 2
+ #define SUPERIO_UART_PM_REG UBPW
+ #define SUPERIO_UART_PM_VAL 0
+ #define SUPERIO_UART_PM_LDN PNP_NO_LDN_CHANGE
+ #include <superio/acpi/pnp_uart.asl>
+#endif
+
+#ifdef F81803A_SHOW_PME
+ #undef SUPERIO_PME_LDN
+ #define SUPERIO_PME_LDN 0x0A
+
+ OperationRegion(APCx, SystemIO, APC5, 0x01)
+ Field(APCx, ByteAcc, Nolock, Preserve) /* bits in PME ACPI CONTROL Reg 5*/
+ {
+ Offset(0x00), /*Control Reg 5 */
+ , 7,
+ PSIN, 1 /* PSIN_FLAG */
+ }
+
+ /* routine to clear PSIN_FLAG in ACPI_CONTROL_REG_5 of SIO */
+ Method(CPSI, 0, Serialized)
+ {
+ /* DBG0("SIO CPSI")*/
+ ENTER_CONFIG_MODE(SUPERIO_PME_LDN)
+ Store(1, PSIN)
+ EXIT_CONFIG_MODE()
+ }
+#endif
+
+}
diff --git a/src/superio/fintek/f81803a/chip.h b/src/superio/fintek/f81803a/chip.h
deleted file mode 100644
index 063f746..0000000
--- a/src/superio/fintek/f81803a/chip.h
+++ /dev/null
@@ -1,63 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2014 Edward O'Callaghan <eocallaghan at alterapraxis.com>
- * Copyright (C) 2017 Nicola Corna <nicola at corna.info>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef SUPERIO_FINTEK_F81803A_CHIP_H
-#define SUPERIO_FINTEK_F81803A_CHIP_H
-
-#include <stdint.h>
-
-/* register in Fintek F81803A */
-#define LDN_REG 0x07
-
-/* Global Control Registers */
-#define CLOCK_SELECT_REG 0x26
-#define FUNC_PROG_SELECT (1<<3)
-#define CONFIG_PORT_SELECT_REG 0x27
-
-#define TSI_LEVEL_SELECT_REG 0x28 /* FUNC_PROG_SEL = 0 */
-#define TSI_PIN_SELECT_REG 0x28 /* FUNC_PROG_SEL = 1 */
-#define MULTI_FUNC_SEL_REG1 0x29
-#define MULTI_FUNC_SEL_REG2 0x2A
-#define MULTI_FUNC_SEL_REG3 0x2B
-#define MULTI_FUNC_SEL_REG4 0x2C
-#define WAKEUP_CONTROL_REG 0x2d
-
-/* LUN A - PMZE, ACPI, ERP */
-#define PME_DEVICE_ENABLE_REG 0x30
-#define PME_ENABLE (1<<0)
-#define PME_ERP_ENABLE_REG 0xE0
-#define ERP_ENABLE (1<<7)
-#define ERP_PME_EN (1<<1)
-#define ERP_PSOUT_EN (1<<0)
-#define PME_ERP_CONTROL_1_REG 0xE1
-#define PME_ERP_CONTROL_2_REG 0xE2
-#define PME_ERP_PSIN_DEBOUNCE_REG 0xE3
-#define PME_ERP_WAKEUP_ENABLE_REG 0xE8
-#define PME_ERP_MODE_SELECT_REG 0xEC
-#define PME_EVENT_ENABLE_1_REG 0xF0
-#define PME_EVENT_STATUS_1_REG 0xF1
-#define PME_EVENT_ENABLE_2_REG 0xF2
-#define PME_EVENT_STATUS_2_REG 0xF3
-#define PME_ACPI_CONTROL_1_REG 0xF4
-#define PME_ACPI_CONTROL_2_REG 0xF5
-#define PME_ACPI_CONTROL_3_REG 0xF6
-#define PME_ACPI_CONTROL_4_REG 0xF7
-#define PME_ACPI_CONTROL_5_REG 0xFB
-#define PME_ACPI_CONTROL_6_REG 0xFC
-
-
-#endif /* SUPERIO_FINTEK_F81803A_CHIP_H */
diff --git a/src/superio/fintek/f81803a/f81803a.h b/src/superio/fintek/f81803a/f81803a.h
index 9e2055c..a955d46 100644
--- a/src/superio/fintek/f81803a/f81803a.h
+++ b/src/superio/fintek/f81803a/f81803a.h
@@ -22,15 +22,53 @@
#ifndef SUPERIO_FINTEK_F81803_H
#define SUPERIO_FINTEK_F81803_H
-/* Logical Device Numbers (LDN). */
-#define F81803A_SP1 0x01 /* UART1 */
-#define F81803A_SP2 0x02 /* UART2 */
-#define F81803A_HWM 0x04 /* Hardware Monitor */
-#define F81803A_KBC 0x05 /* Keyboard/Mouse */
+/* Logical Device Numbers (LDN) */
+#define F81803A_SP1 0x01 /* UART1 */
+#define F81803A_SP2 0x02 /* UART2 */
+#define F81803A_HWM 0x04 /* Hardware Monitor */
+#define F81803A_KBC 0x05 /* Keyboard/Mouse */
#define F81803A_GPIO 0x06 /* General Purpose I/O (GPIO) */
-#define F81803A_WDT 0x07 /* Watch Dog Timer */
-#define F81803A_PME 0x0a /* Power Management Events (PME) */
+#define F81803A_WDT 0x07 /* Watch Dog Timer */
+#define F81803A_PME 0x0a /* Power Management Events (PME) */
+
+/* registers in Fintek F81803A */
+#define LDN_REG 0x07
+
+/* Global Control Registers */
+#define CLOCK_SELECT_REG 0x26
+#define FUNC_PROG_SELECT (1<<3)
+#define CONFIG_PORT_SELECT_REG 0x27
+
+#define TSI_LEVEL_SELECT_REG 0x28 /* FUNC_PROG_SEL = 0 */
+#define TSI_PIN_SELECT_REG 0x28 /* FUNC_PROG_SEL = 1 */
+#define MULTI_FUNC_SEL_REG1 0x29
+#define MULTI_FUNC_SEL_REG2 0x2A
+#define MULTI_FUNC_SEL_REG3 0x2B
+#define MULTI_FUNC_SEL_REG 0x2C
+#define WAKEUP_CONTROL_REG 0x2d
+
+/* LUN A - PME, ACPI, ERP */
+#define PME_DEVICE_ENABLE_REG 0x30
+#define PME_ENABLE (1<<0)
+#define PME_ERP_ENABLE_REG 0xE0
+#define ERP_ENABLE (1<<7)
+#define ERP_PME_EN (1<<1)
+#define ERP_PSOUT_EN (1<<0)
+#define PME_ERP_CONTROL_1_REG 0xE1
+#define PME_ERP_CONTROL_2_REG 0xE2
+#define PME_ERP_PSIN_DEBOUNCE_REG 0xE3
+#define PME_ERP_WAKEUP_ENABLE_REG 0xE8
+#define PME_ERP_MODE_SELECT_REG 0xEC
+#define PME_EVENT_ENABLE_1_REG 0xF0
+#define PME_EVENT_STATUS_1_REG 0xF1
+#define PME_EVENT_ENABLE_2_REG 0xF2
+#define PME_EVENT_STATUS_2_REG 0xF3
+#define PME_ACPI_CONTROL_1_REG 0xF4
+#define PME_ACPI_CONTROL_2_REG 0xF5
+#define PME_ACPI_CONTROL_3_REG 0xF6
+#define PME_ACPI_CONTROL_4_REG 0xF7
+#define PME_ACPI_CONTROL_5_REG 0xFB
+#define PME_ACPI_CONTROL_6_REG 0xFC
#endif /* SUPERIO_FINTEK_F81803_H */
-#include "fintek_internal.h"
diff --git a/src/superio/fintek/f81803a/f81803a_pme.c b/src/superio/fintek/f81803a/f81803a_pme.c
deleted file mode 100644
index 2223212..0000000
--- a/src/superio/fintek/f81803a/f81803a_pme.c
+++ /dev/null
@@ -1,39 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2014 Edward O'Callaghan <eocallaghan at alterapraxis.com>
- * Copyright (C) 2017 Nicola Corna <nicola at corna.info>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <arch/io.h>
-#include <console/console.h>
-#include <device/device.h>
-#include <device/pnp.h>
-#include "f81803a.h"
-
-
-
-void f81803a_pme_init(struct device *dev)
-{
-
- printk(BIOS_INFO, "F81803A PME: Init.\n");
-
- pnp_enter_conf_mode(dev);
- pnp_write_config(dev, LDN_REG, F81803A_PME);
-
- /* enable ERP function*/
- /* also set PSIN to generate PSOUT*/
- pnp_write_config(dev, PME_ERP_ENABLE_REG,ERP_ENABLE | ERP_PSOUT_EN);
-
- pnp_exit_conf_mode(dev);
-}
diff --git a/src/superio/fintek/f81803a/fintek_internal.h b/src/superio/fintek/f81803a/fintek_internal.h
deleted file mode 100644
index 5b8d275..0000000
--- a/src/superio/fintek/f81803a/fintek_internal.h
+++ /dev/null
@@ -1,32 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2014 Edward O'Callaghan <eocallaghan at alterapraxis.com>
- * Copyright (C) 2017 Nicola Corna <nicola at corna.info>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef SUPERIO_FINTEK_F81803A_INTERNAL_H
-#define SUPERIO_FINTEK_F81803A_INTERNAL_H
-
-#include <arch/io.h>
-#include <device/pnp.h>
-#include "chip.h"
-
-struct f81803a_reg_tab
-{
- const char *reg_name;
- uint8_t reg;
-};
-void f81803a_pme_init(struct device *dev);
-void f81803a_reg_dump(struct device *dev, struct f81803a_reg_tab *tab);
-#endif /* SUPERIO_FINTEK_F81803A_INTERNAL_H */
diff --git a/src/superio/fintek/f81803a/superio.c b/src/superio/fintek/f81803a/superio.c
index 3f5636a..3ebca87 100644
--- a/src/superio/fintek/f81803a/superio.c
+++ b/src/superio/fintek/f81803a/superio.c
@@ -23,118 +23,39 @@
#include <pc80/keyboard.h>
#include "f81803a.h"
-#ifdef F81803A_REGDUMP
-/* for Debug */
-static struct f81803a_reg_tab f81803a_pme_regs1[] = {
-
- { "CLOCK_SELECT_REG", CLOCK_SELECT_REG },
- { "CONFIG_PORT_SELECT_REG", CONFIG_PORT_SELECT_REG },
- { "TSI_PIN_SELECT_REG", TSI_PIN_SELECT_REG },
- { NULL, 0 }
-};
-
-
-static struct f81803a_reg_tab f81803a_pme_regs2[] = {
- { "TSI_LEVEL_SELECT_REG", TSI_LEVEL_SELECT_REG },
- { "MULTI_FUNC_SEL_REG1", MULTI_FUNC_SEL_REG1 },
- { "MULTI_FUNC_SEL_REG2", MULTI_FUNC_SEL_REG2 },
- { "MULTI_FUNC_SEL_REG3", MULTI_FUNC_SEL_REG3 },
- { "MULTI_FUNC_SEL_REG4", MULTI_FUNC_SEL_REG4 },
- { "WAKEUP_CONTROL_REG", WAKEUP_CONTROL_REG },
- { "PME_DEVICE_ENABLE_REG", PME_DEVICE_ENABLE_REG },
- { "PME_ERP_ENABLE_REG", PME_ERP_ENABLE_REG },
- { "PME_ERP_CONTROL_1_REG", PME_ERP_CONTROL_1_REG },
- { "PME_ERP_CONTROL_2_REG", PME_ERP_CONTROL_2_REG },
- { "PME_ERP_PSIN_DEBOUNCE_REG", PME_ERP_PSIN_DEBOUNCE_REG },
- { "PME_ERP_WAKEUP_ENABLE_REG", PME_ERP_WAKEUP_ENABLE_REG },
- { "PME_EVENT_ENABLE_1_REG", PME_EVENT_ENABLE_1_REG },
- { "PME_EVENT_ENABLE_2_REG", PME_EVENT_ENABLE_2_REG },
- { "PME_ACPI_CONTROL_1_REG", PME_ACPI_CONTROL_1_REG },
- { "PME_ACPI_CONTROL_2_REG", PME_ACPI_CONTROL_2_REG },
- { "PME_ACPI_CONTROL_3_REG", PME_ACPI_CONTROL_3_REG },
- { "PME_ACPI_CONTROL_4_REG", PME_ACPI_CONTROL_4_REG },
- { "PME_ACPI_CONTROL_5_REG", PME_ACPI_CONTROL_5_REG },
- { "PME_ACPI_CONTROL_6_REG", PME_ACPI_CONTROL_6_REG },
- { NULL, 0 }
-};
-
-void f81803a_reg_dump(struct device *dev, struct f81803a_reg_tab *tab)
+static void f81803a_pme_init(struct device *dev)
{
- uint8_t val;
- for (; tab->reg_name; tab++)
- {
- val = pnp_read_config(dev, tab->reg);
- printk(BIOS_INFO, " %02X %s %02X\n", tab->reg, tab->reg_name, val & 0xff);
- }
-
+ pnp_enter_conf_mode(dev);
+ pnp_write_config(dev, LDN_REG, F81803A_PME);
+ /* enable ERP function*/
+ /* also set PSIN to generate PSOUT*/
+ pnp_write_config(dev, PME_ERP_ENABLE_REG, ERP_ENABLE | ERP_PSOUT_EN);
+ pnp_exit_conf_mode(dev);
}
-static void f81803a_pme_reg_dump(struct device *dev, const char *s)
-{
- uint8_t save_clock_select;
- printk(BIOS_INFO, "\nF81803A PME: Regs %s\n", s);
- pnp_enter_conf_mode(dev);
- pnp_write_config(dev, LDN_REG, F81803A_PME);
- /*
- * this is done with two tables as FUNC_PROG_SEL in CLOCK_SELECT_REG
- * is used as a bank select register for the TSI registers index 28
- * We assume that FUNC_PROG_SELECT is 0 for now
- *
- * Note the actual writeup for FUNC_PROG_SEL on page 52 say:
- * "Index 0x29, 0x2B and 0x2C bank select register"
- * However this is not the case and only reg 28 appears to be affected
- * TODO: Confirm this
- */
- /* read CLOCK_SELECT_REGISTER and save it */
- save_clock_select = pnp_read_config(dev, CLOCK_SELECT_REG);
- /* set FUNC_PROG_SELECT so we read TSI_PIN_SELECT*/
- pnp_write_config(dev, CLOCK_SELECT_REG, save_clock_select | FUNC_PROG_SELECT);
- f81803a_reg_dump(dev, f81803a_pme_regs1);
-
- /* now set it back to 0 and read the rest*/
-
- pnp_write_config(dev, CLOCK_SELECT_REG, save_clock_select);
- f81803a_reg_dump(dev, f81803a_pme_regs2);
-
- pnp_exit_conf_mode(dev);
- printk(BIOS_INFO, "\nF81803A PME: Regs Done %s\n", s);
-}
-#endif
static void f81803a_init(struct device *dev)
{
-
- printk(BIOS_INFO, "F81803A_INIT.\n");
-
if (!dev->enabled)
return;
-
switch (dev->path.pnp.device) {
/* TODO: Might potentially need code for HWM or FDC etc. */
case F81803A_KBC:
pc_keyboard_init(NO_AUX_DEVICE);
break;
- case F81803A_PME:
-#ifdef F81803A_REGDUMP
- f81803a_pme_reg_dump(dev,"before");
-#endif
- f81803a_pme_init(dev);
-#ifdef F81803A_REGDUMP
- f81803a_pme_reg_dump(dev, "after");
-#endif
- break;
-
-
+ case F81803A_PME:
+ f81803a_pme_init(dev);
+ break;
}
}
static struct device_operations ops = {
- .read_resources = pnp_read_resources,
- .set_resources = pnp_set_resources,
- .enable_resources = pnp_enable_resources,
- .enable = pnp_alt_enable,
- .init = f81803a_init,
- .ops_pnp_mode = &pnp_conf_mode_8787_aa,
+ .read_resources = pnp_read_resources,
+ .set_resources = pnp_set_resources,
+ .enable_resources = pnp_enable_resources,
+ .enable = pnp_alt_enable,
+ .init = f81803a_init,
+ .ops_pnp_mode = &pnp_conf_mode_8787_aa,
};
static struct pnp_info pnp_dev_info[] = {
@@ -155,6 +76,5 @@
}
struct chip_operations superio_fintek_f81803a_ops = {
- CHIP_NAME("Fintek F81803A Super I/O")
.enable_dev = enable_dev
};
--
To view, visit https://review.coreboot.org/21047
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Ib4b078a590ba27f698dad84d6bd6237c8331e60f
Gerrit-Change-Number: 21047
Gerrit-PatchSet: 1
Gerrit-Owner: John E. Kabat <sljkrr at gmail.com>
Gerrit-Reviewer: John E. Kabat Jr. <john.kabat at scarletltd.com>
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