<p>John E. Kabat would like John E. Kabat Jr. to <strong>review</strong> this change.</p><p><a href="https://review.coreboot.org/21047">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">amd/padmelon: Adding more Fintek F81803A files<br><br>This reorganizes the Fintek F81803A files and adds new features.<br>superio.asl add access to PME ACPI Control Register 5 for clearing<br>the PSIN_FLAG. Method CPSI() is used by asl power button code to clear this.<br>f81803a.h consolidates all the bit and register definition in one place.<br>superio.c consolidates all the initialization functions.<br>Superio.asl moved to the acpi directory.<br>chip.h fintek_internal.h and f81803a_pme.c have been folded into other<br>files and are no longer needed<br><br>Change-Id: Ib4b078a590ba27f698dad84d6bd6237c8331e60f<br>Signed-off-by: John Kabat <john.kabat@scarletltd.com><br>---<br>M src/superio/fintek/f81803a/Makefile.inc<br>A src/superio/fintek/f81803a/acpi/superio.asl<br>D src/superio/fintek/f81803a/chip.h<br>M src/superio/fintek/f81803a/f81803a.h<br>D src/superio/fintek/f81803a/f81803a_pme.c<br>D src/superio/fintek/f81803a/fintek_internal.h<br>M src/superio/fintek/f81803a/superio.c<br>7 files changed, 217 insertions(+), 239 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/21047/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/superio/fintek/f81803a/Makefile.inc b/src/superio/fintek/f81803a/Makefile.inc<br>index 372de05..9156bf9 100644<br>--- a/src/superio/fintek/f81803a/Makefile.inc<br>+++ b/src/superio/fintek/f81803a/Makefile.inc<br>@@ -15,4 +15,3 @@<br> ##<br> <br> ramstage-$(CONFIG_SUPERIO_FINTEK_F81803A) += superio.c<br>-ramstage-$(CONFIG_SUPERIO_FINTEK_F81803A) += f81803a_pme.c<br>diff --git a/src/superio/fintek/f81803a/acpi/superio.asl b/src/superio/fintek/f81803a/acpi/superio.asl<br>new file mode 100644<br>index 0000000..7568131<br>--- /dev/null<br>+++ b/src/superio/fintek/f81803a/acpi/superio.asl<br>@@ -0,0 +1,155 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright (C) 2011 Christoph Grenz <christophg+cb@grenz-bonn.de><br>+ * Copyright (C) 2013 secunet Security Networks AG<br>+ *<br>+ * This program is free software; you can redistribute it and/or modify<br>+ * it under the terms of the GNU General Public License as published by<br>+ * the Free Software Foundation; version 2 of the License.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ */<br>+<br>+/*<br>+ * Include this file into a mainboard's DSDT _SB device tree and it will<br>+ * expose the F81803A SuperIO and some of its functionality.<br>+ *<br>+ * It allows the change of IO ports, IRQs and DMA settings on logical<br>+ * devices, disabling and reenabling logical devices and controlling power<br>+ * saving mode on logical devices or the whole chip.<br>+ *<br>+ * LDN State<br>+ * 0x1 UARTA Implemented, partially tested<br>+ * 0x2 UARTB UART only, partially tested<br>+ * 0x4 HWM Not implemented<br>+ * 0x5 KBC Implemented, untested<br>+ * 0x6 GPIO6 Not implemented<br>+ * 0x7 WDT0&PLED Not implemented<br>+ * 0xa ACPI/PME/ERP Partially implemented<br>+ *<br>+ * Controllable through preprocessor defines:<br>+ * SUPERIO_DEV Device identifier for this SIO (e.g. SIO0)<br>+ * SUPERIO_PNP_BASE I/o address of the first PnP configuration register<br>+ * F81803A_SHOW_UARTA If defined, UARTA will be exposed.<br>+ * F81803A_SHOW_UARTB If defined, UARTB will be exposed.<br>+ * F81803A_SHOW_KBC If defined, the KBC will be exposed.<br>+ * F81803A_SHOW_PS2M If defined, PS/2 mouse support will be exposed.<br>+ * F81803A_SHOW_HWMON If defined, the hardware monitor will be exposed.<br>+ * F81803A_SHOW_PME If defined, the PME/EARP/ACPI will be exposed.<br>+ */<br>+#undef SUPERIO_DEV<br>+#define SUPERIO_DEV SIO0<br>+#undef SUPERIO_CHIP_NAME<br>+#define SUPERIO_CHIP_NAME F81803A<br>+#define SUPERIO_PNP_BASE 0x4E<br>+#define F81803A_SHOW_PME<br>+#include <superio/acpi/pnp.asl><br>+<br>+<br>+<br>+Device(SUPERIO_DEV) {<br>+ Name (_HID, EisaId("PNP0A05"))<br>+ Name (_STR, Unicode("Fintek F81803A Super I/O"))<br>+ Name (_UID, SUPERIO_UID(SUPERIO_DEV,))<br>+<br>+ /* Mutex for accesses to the configuration ports */<br>+ Mutex(CRMX, 1)<br>+<br>+ /* SuperIO configuration ports */<br>+ OperationRegion (CREG, SystemIO, SUPERIO_PNP_BASE, 0x02)<br>+ Field (CREG, ByteAcc, NoLock, Preserve)<br>+ {<br>+ PNP_ADDR_REG, 8,<br>+ PNP_DATA_REG, 8<br>+ }<br>+ IndexField (ADDR, DATA, ByteAcc, NoLock, Preserve)<br>+ {<br>+ Offset (0x07),<br>+ PNP_LOGICAL_DEVICE, 8, /* Logical device selector */<br>+ Offset (0x30),<br>+ PNP_DEVICE_ACTIVE, 1, /* Logical device activation */<br>+ Offset (0x60),<br>+ PNP_IO0_HIGH_BYTE, 8, /* First I/O port base - high byte */<br>+ PNP_IO0_LOW_BYTE, 8, /* First I/O port base - low byte */<br>+ Offset (0x62),<br>+ PNP_IO1_HIGH_BYTE, 8, /* Second I/O port base - high byte */<br>+ PNP_IO1_LOW_BYTE, 8, /* Second I/O port base - low byte */<br>+ Offset (0x70),<br>+ PNP_IRQ0, 8, /* First IRQ */<br>+ offset(0xFB),<br>+ APC5, 8, /* PME ACPI Control Register 5 */<br>+ }<br>+<br>+ Method(_CRS)<br>+ {<br>+ /* Announce the used i/o ports to the OS */<br>+ Return (ResourceTemplate () {<br>+ IO (Decode16, SUPERIO_PNP_BASE, SUPERIO_PNP_BASE, 0x01, 0x02)<br>+ })<br>+ }<br>+<br>+ #undef PNP_ENTER_MAGIC_1ST<br>+ #undef PNP_ENTER_MAGIC_2ND<br>+ #undef PNP_ENTER_MAGIC_3RD<br>+ #undef PNP_ENTER_MAGIC_4TH<br>+ #undef PNP_EXIT_MAGIC_1ST<br>+ #undef PNP_EXIT_SPECIAL_REG<br>+ #undef PNP_EXIT_SPECIAL_VAL<br>+ #define PNP_ENTER_MAGIC_1ST 0x87<br>+ #define PNP_ENTER_MAGIC_2ND 0x87<br>+ #define PNP_EXIT_MAGIC_1ST 0xaa<br>+ #include <superio/acpi/pnp_config.asl><br>+<br>+#ifdef F81803A_SHOW_UARTA<br>+ #undef SUPERIO_UART_LDN<br>+ #undef SUPERIO_UART_DDN<br>+ #undef SUPERIO_UART_PM_REG<br>+ #undef SUPERIO_UART_PM_VAL<br>+ #undef SUPERIO_UART_PM_LDN<br>+ #define SUPERIO_UART_LDN 1<br>+ #define SUPERIO_UART_PM_REG UAPW<br>+ #define SUPERIO_UART_PM_VAL 0<br>+ #define SUPERIO_UART_PM_LDN PNP_NO_LDN_CHANGE<br>+ #include <superio/acpi/pnp_uart.asl><br>+#endif<br>+<br>+#ifdef F81803A_SHOW_UARTB<br>+ #undef SUPERIO_UART_LDN<br>+ #undef SUPERIO_UART_DDN<br>+ #undef SUPERIO_UART_PM_REG<br>+ #undef SUPERIO_UART_PM_VAL<br>+ #undef SUPERIO_UART_PM_LDN<br>+ #define SUPERIO_UART_LDN 2<br>+ #define SUPERIO_UART_PM_REG UBPW<br>+ #define SUPERIO_UART_PM_VAL 0<br>+ #define SUPERIO_UART_PM_LDN PNP_NO_LDN_CHANGE<br>+ #include <superio/acpi/pnp_uart.asl><br>+#endif<br>+<br>+#ifdef F81803A_SHOW_PME<br>+ #undef SUPERIO_PME_LDN<br>+ #define SUPERIO_PME_LDN 0x0A<br>+<br>+ OperationRegion(APCx, SystemIO, APC5, 0x01)<br>+ Field(APCx, ByteAcc, Nolock, Preserve) /* bits in PME ACPI CONTROL Reg 5*/<br>+ {<br>+ Offset(0x00), /*Control Reg 5 */<br>+ , 7,<br>+ PSIN, 1 /* PSIN_FLAG */<br>+ }<br>+<br>+ /* routine to clear PSIN_FLAG in ACPI_CONTROL_REG_5 of SIO */<br>+ Method(CPSI, 0, Serialized)<br>+ {<br>+ /* DBG0("SIO CPSI")*/<br>+ ENTER_CONFIG_MODE(SUPERIO_PME_LDN)<br>+ Store(1, PSIN)<br>+ EXIT_CONFIG_MODE()<br>+ }<br>+#endif<br>+<br>+}<br>diff --git a/src/superio/fintek/f81803a/chip.h b/src/superio/fintek/f81803a/chip.h<br>deleted file mode 100644<br>index 063f746..0000000<br>--- a/src/superio/fintek/f81803a/chip.h<br>+++ /dev/null<br>@@ -1,63 +0,0 @@<br>-/*<br>- * This file is part of the coreboot project.<br>- *<br>- * Copyright (C) 2014 Edward O'Callaghan <eocallaghan@alterapraxis.com><br>- * Copyright (C) 2017 Nicola Corna <nicola@corna.info><br>- *<br>- * This program is free software; you can redistribute it and/or modify<br>- * it under the terms of the GNU General Public License as published by<br>- * the Free Software Foundation; either version 2 of the License, or<br>- * (at your option) any later version.<br>- *<br>- * This program is distributed in the hope that it will be useful,<br>- * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>- * GNU General Public License for more details.<br>- */<br>-<br>-#ifndef SUPERIO_FINTEK_F81803A_CHIP_H<br>-#define SUPERIO_FINTEK_F81803A_CHIP_H<br>-<br>-#include <stdint.h><br>-<br>-/* register in Fintek F81803A */<br>-#define LDN_REG 0x07<br>-<br>-/* Global Control Registers */<br>-#define CLOCK_SELECT_REG 0x26<br>-#define FUNC_PROG_SELECT (1<<3)<br>-#define CONFIG_PORT_SELECT_REG 0x27<br>-<br>-#define TSI_LEVEL_SELECT_REG 0x28 /* FUNC_PROG_SEL = 0 */<br>-#define TSI_PIN_SELECT_REG 0x28 /* FUNC_PROG_SEL = 1 */<br>-#define MULTI_FUNC_SEL_REG1 0x29<br>-#define MULTI_FUNC_SEL_REG2 0x2A<br>-#define MULTI_FUNC_SEL_REG3 0x2B<br>-#define MULTI_FUNC_SEL_REG4 0x2C<br>-#define WAKEUP_CONTROL_REG 0x2d<br>-<br>-/* LUN A - PMZE, ACPI, ERP */<br>-#define PME_DEVICE_ENABLE_REG 0x30<br>-#define PME_ENABLE (1<<0)<br>-#define PME_ERP_ENABLE_REG 0xE0<br>-#define ERP_ENABLE (1<<7)<br>-#define ERP_PME_EN (1<<1)<br>-#define ERP_PSOUT_EN (1<<0)<br>-#define PME_ERP_CONTROL_1_REG 0xE1<br>-#define PME_ERP_CONTROL_2_REG 0xE2<br>-#define PME_ERP_PSIN_DEBOUNCE_REG 0xE3<br>-#define PME_ERP_WAKEUP_ENABLE_REG 0xE8<br>-#define PME_ERP_MODE_SELECT_REG 0xEC<br>-#define PME_EVENT_ENABLE_1_REG 0xF0<br>-#define PME_EVENT_STATUS_1_REG 0xF1<br>-#define PME_EVENT_ENABLE_2_REG 0xF2<br>-#define PME_EVENT_STATUS_2_REG 0xF3<br>-#define PME_ACPI_CONTROL_1_REG 0xF4<br>-#define PME_ACPI_CONTROL_2_REG 0xF5<br>-#define PME_ACPI_CONTROL_3_REG 0xF6<br>-#define PME_ACPI_CONTROL_4_REG 0xF7<br>-#define PME_ACPI_CONTROL_5_REG 0xFB<br>-#define PME_ACPI_CONTROL_6_REG 0xFC<br>-<br>-<br>-#endif /* SUPERIO_FINTEK_F81803A_CHIP_H */<br>diff --git a/src/superio/fintek/f81803a/f81803a.h b/src/superio/fintek/f81803a/f81803a.h<br>index 9e2055c..a955d46 100644<br>--- a/src/superio/fintek/f81803a/f81803a.h<br>+++ b/src/superio/fintek/f81803a/f81803a.h<br>@@ -22,15 +22,53 @@<br> #ifndef SUPERIO_FINTEK_F81803_H<br> #define SUPERIO_FINTEK_F81803_H<br> <br>-/* Logical Device Numbers (LDN). */<br>-#define F81803A_SP1 0x01 /* UART1 */<br>-#define F81803A_SP2 0x02 /* UART2 */<br>-#define F81803A_HWM 0x04 /* Hardware Monitor */<br>-#define F81803A_KBC 0x05 /* Keyboard/Mouse */<br>+/* Logical Device Numbers (LDN) */<br>+#define F81803A_SP1 0x01 /* UART1 */<br>+#define F81803A_SP2 0x02 /* UART2 */<br>+#define F81803A_HWM 0x04 /* Hardware Monitor */<br>+#define F81803A_KBC 0x05 /* Keyboard/Mouse */<br> #define F81803A_GPIO 0x06 /* General Purpose I/O (GPIO) */<br>-#define F81803A_WDT 0x07 /* Watch Dog Timer */<br>-#define F81803A_PME 0x0a /* Power Management Events (PME) */<br>+#define F81803A_WDT 0x07 /* Watch Dog Timer */<br>+#define F81803A_PME 0x0a /* Power Management Events (PME) */<br>+<br>+/* registers in Fintek F81803A */<br>+#define LDN_REG 0x07<br>+<br>+/* Global Control Registers */<br>+#define CLOCK_SELECT_REG 0x26<br>+#define FUNC_PROG_SELECT (1<<3)<br>+#define CONFIG_PORT_SELECT_REG 0x27<br>+<br>+#define TSI_LEVEL_SELECT_REG 0x28 /* FUNC_PROG_SEL = 0 */<br>+#define TSI_PIN_SELECT_REG 0x28 /* FUNC_PROG_SEL = 1 */<br>+#define MULTI_FUNC_SEL_REG1 0x29<br>+#define MULTI_FUNC_SEL_REG2 0x2A<br>+#define MULTI_FUNC_SEL_REG3 0x2B<br>+#define MULTI_FUNC_SEL_REG 0x2C<br>+#define WAKEUP_CONTROL_REG 0x2d<br>+<br>+/* LUN A - PME, ACPI, ERP */<br>+#define PME_DEVICE_ENABLE_REG 0x30<br>+#define PME_ENABLE (1<<0)<br>+#define PME_ERP_ENABLE_REG 0xE0<br>+#define ERP_ENABLE (1<<7)<br>+#define ERP_PME_EN (1<<1)<br>+#define ERP_PSOUT_EN (1<<0)<br>+#define PME_ERP_CONTROL_1_REG 0xE1<br>+#define PME_ERP_CONTROL_2_REG 0xE2<br>+#define PME_ERP_PSIN_DEBOUNCE_REG 0xE3<br>+#define PME_ERP_WAKEUP_ENABLE_REG 0xE8<br>+#define PME_ERP_MODE_SELECT_REG 0xEC<br>+#define PME_EVENT_ENABLE_1_REG 0xF0<br>+#define PME_EVENT_STATUS_1_REG 0xF1<br>+#define PME_EVENT_ENABLE_2_REG 0xF2<br>+#define PME_EVENT_STATUS_2_REG 0xF3<br>+#define PME_ACPI_CONTROL_1_REG 0xF4<br>+#define PME_ACPI_CONTROL_2_REG 0xF5<br>+#define PME_ACPI_CONTROL_3_REG 0xF6<br>+#define PME_ACPI_CONTROL_4_REG 0xF7<br>+#define PME_ACPI_CONTROL_5_REG 0xFB<br>+#define PME_ACPI_CONTROL_6_REG 0xFC<br> <br> #endif /* SUPERIO_FINTEK_F81803_H */<br>-#include "fintek_internal.h"<br> <br>diff --git a/src/superio/fintek/f81803a/f81803a_pme.c b/src/superio/fintek/f81803a/f81803a_pme.c<br>deleted file mode 100644<br>index 2223212..0000000<br>--- a/src/superio/fintek/f81803a/f81803a_pme.c<br>+++ /dev/null<br>@@ -1,39 +0,0 @@<br>-/*<br>- * This file is part of the coreboot project.<br>- *<br>- * Copyright (C) 2014 Edward O'Callaghan <eocallaghan@alterapraxis.com><br>- * Copyright (C) 2017 Nicola Corna <nicola@corna.info><br>- *<br>- * This program is free software; you can redistribute it and/or modify<br>- * it under the terms of the GNU General Public License as published by<br>- * the Free Software Foundation; either version 2 of the License, or<br>- * (at your option) any later version.<br>- *<br>- * This program is distributed in the hope that it will be useful,<br>- * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>- * GNU General Public License for more details.<br>- */<br>-<br>-#include <arch/io.h><br>-#include <console/console.h><br>-#include <device/device.h><br>-#include <device/pnp.h><br>-#include "f81803a.h"<br>-<br>-<br>-<br>-void f81803a_pme_init(struct device *dev)<br>-{<br>-<br>- printk(BIOS_INFO, "F81803A PME: Init.\n");<br>-<br>- pnp_enter_conf_mode(dev);<br>- pnp_write_config(dev, LDN_REG, F81803A_PME);<br>-<br>- /* enable ERP function*/<br>- /* also set PSIN to generate PSOUT*/<br>- pnp_write_config(dev, PME_ERP_ENABLE_REG,ERP_ENABLE | ERP_PSOUT_EN);<br>-<br>- pnp_exit_conf_mode(dev);<br>-}<br>diff --git a/src/superio/fintek/f81803a/fintek_internal.h b/src/superio/fintek/f81803a/fintek_internal.h<br>deleted file mode 100644<br>index 5b8d275..0000000<br>--- a/src/superio/fintek/f81803a/fintek_internal.h<br>+++ /dev/null<br>@@ -1,32 +0,0 @@<br>-/*<br>- * This file is part of the coreboot project.<br>- *<br>- * Copyright (C) 2014 Edward O'Callaghan <eocallaghan@alterapraxis.com><br>- * Copyright (C) 2017 Nicola Corna <nicola@corna.info><br>- *<br>- * This program is free software; you can redistribute it and/or modify<br>- * it under the terms of the GNU General Public License as published by<br>- * the Free Software Foundation; either version 2 of the License, or<br>- * (at your option) any later version.<br>- *<br>- * This program is distributed in the hope that it will be useful,<br>- * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>- * GNU General Public License for more details.<br>- */<br>-<br>-#ifndef SUPERIO_FINTEK_F81803A_INTERNAL_H<br>-#define SUPERIO_FINTEK_F81803A_INTERNAL_H<br>-<br>-#include <arch/io.h><br>-#include <device/pnp.h><br>-#include "chip.h"<br>-<br>-struct f81803a_reg_tab<br>-{<br>- const char *reg_name;<br>- uint8_t reg;<br>-};<br>-void f81803a_pme_init(struct device *dev);<br>-void f81803a_reg_dump(struct device *dev, struct f81803a_reg_tab *tab);<br>-#endif /* SUPERIO_FINTEK_F81803A_INTERNAL_H */<br>diff --git a/src/superio/fintek/f81803a/superio.c b/src/superio/fintek/f81803a/superio.c<br>index 3f5636a..3ebca87 100644<br>--- a/src/superio/fintek/f81803a/superio.c<br>+++ b/src/superio/fintek/f81803a/superio.c<br>@@ -23,118 +23,39 @@<br> #include <pc80/keyboard.h><br> #include "f81803a.h"<br> <br>-#ifdef F81803A_REGDUMP<br>-/* for Debug */<br>-static struct f81803a_reg_tab f81803a_pme_regs1[] = {<br>-<br>- { "CLOCK_SELECT_REG", CLOCK_SELECT_REG },<br>- { "CONFIG_PORT_SELECT_REG", CONFIG_PORT_SELECT_REG },<br>- { "TSI_PIN_SELECT_REG", TSI_PIN_SELECT_REG },<br>- { NULL, 0 }<br>-};<br>-<br>-<br>-static struct f81803a_reg_tab f81803a_pme_regs2[] = {<br>- { "TSI_LEVEL_SELECT_REG", TSI_LEVEL_SELECT_REG },<br>- { "MULTI_FUNC_SEL_REG1", MULTI_FUNC_SEL_REG1 },<br>- { "MULTI_FUNC_SEL_REG2", MULTI_FUNC_SEL_REG2 },<br>- { "MULTI_FUNC_SEL_REG3", MULTI_FUNC_SEL_REG3 },<br>- { "MULTI_FUNC_SEL_REG4", MULTI_FUNC_SEL_REG4 },<br>- { "WAKEUP_CONTROL_REG", WAKEUP_CONTROL_REG },<br>- { "PME_DEVICE_ENABLE_REG", PME_DEVICE_ENABLE_REG },<br>- { "PME_ERP_ENABLE_REG", PME_ERP_ENABLE_REG },<br>- { "PME_ERP_CONTROL_1_REG", PME_ERP_CONTROL_1_REG },<br>- { "PME_ERP_CONTROL_2_REG", PME_ERP_CONTROL_2_REG },<br>- { "PME_ERP_PSIN_DEBOUNCE_REG", PME_ERP_PSIN_DEBOUNCE_REG },<br>- { "PME_ERP_WAKEUP_ENABLE_REG", PME_ERP_WAKEUP_ENABLE_REG },<br>- { "PME_EVENT_ENABLE_1_REG", PME_EVENT_ENABLE_1_REG },<br>- { "PME_EVENT_ENABLE_2_REG", PME_EVENT_ENABLE_2_REG },<br>- { "PME_ACPI_CONTROL_1_REG", PME_ACPI_CONTROL_1_REG },<br>- { "PME_ACPI_CONTROL_2_REG", PME_ACPI_CONTROL_2_REG },<br>- { "PME_ACPI_CONTROL_3_REG", PME_ACPI_CONTROL_3_REG },<br>- { "PME_ACPI_CONTROL_4_REG", PME_ACPI_CONTROL_4_REG },<br>- { "PME_ACPI_CONTROL_5_REG", PME_ACPI_CONTROL_5_REG },<br>- { "PME_ACPI_CONTROL_6_REG", PME_ACPI_CONTROL_6_REG },<br>- { NULL, 0 }<br>-};<br>-<br>-void f81803a_reg_dump(struct device *dev, struct f81803a_reg_tab *tab)<br>+static void f81803a_pme_init(struct device *dev)<br> {<br>- uint8_t val;<br>- for (; tab->reg_name; tab++)<br>- {<br>- val = pnp_read_config(dev, tab->reg);<br>- printk(BIOS_INFO, " %02X %s %02X\n", tab->reg, tab->reg_name, val & 0xff);<br>- }<br>-<br>+ pnp_enter_conf_mode(dev);<br>+ pnp_write_config(dev, LDN_REG, F81803A_PME);<br>+ /* enable ERP function*/<br>+ /* also set PSIN to generate PSOUT*/<br>+ pnp_write_config(dev, PME_ERP_ENABLE_REG, ERP_ENABLE | ERP_PSOUT_EN);<br>+ pnp_exit_conf_mode(dev);<br> }<br>-static void f81803a_pme_reg_dump(struct device *dev, const char *s)<br>-{<br>- uint8_t save_clock_select;<br>- printk(BIOS_INFO, "\nF81803A PME: Regs %s\n", s);<br>- pnp_enter_conf_mode(dev);<br>- pnp_write_config(dev, LDN_REG, F81803A_PME);<br>- /*<br>- * this is done with two tables as FUNC_PROG_SEL in CLOCK_SELECT_REG<br>- * is used as a bank select register for the TSI registers index 28<br>- * We assume that FUNC_PROG_SELECT is 0 for now<br>- *<br>- * Note the actual writeup for FUNC_PROG_SEL on page 52 say:<br>- * "Index 0x29, 0x2B and 0x2C bank select register"<br>- * However this is not the case and only reg 28 appears to be affected<br>- * TODO: Confirm this<br>- */<br> <br>- /* read CLOCK_SELECT_REGISTER and save it */<br>- save_clock_select = pnp_read_config(dev, CLOCK_SELECT_REG);<br>- /* set FUNC_PROG_SELECT so we read TSI_PIN_SELECT*/<br>- pnp_write_config(dev, CLOCK_SELECT_REG, save_clock_select | FUNC_PROG_SELECT);<br>- f81803a_reg_dump(dev, f81803a_pme_regs1);<br>-<br>- /* now set it back to 0 and read the rest*/<br>-<br>- pnp_write_config(dev, CLOCK_SELECT_REG, save_clock_select);<br>- f81803a_reg_dump(dev, f81803a_pme_regs2);<br>-<br>- pnp_exit_conf_mode(dev);<br>- printk(BIOS_INFO, "\nF81803A PME: Regs Done %s\n", s);<br>-}<br>-#endif<br> static void f81803a_init(struct device *dev)<br> {<br>-<br>- printk(BIOS_INFO, "F81803A_INIT.\n");<br>-<br> if (!dev->enabled)<br> return;<br>-<br> switch (dev->path.pnp.device) {<br> /* TODO: Might potentially need code for HWM or FDC etc. */<br> case F81803A_KBC:<br> pc_keyboard_init(NO_AUX_DEVICE);<br> break;<br>- case F81803A_PME:<br>-#ifdef F81803A_REGDUMP<br>- f81803a_pme_reg_dump(dev,"before");<br>-#endif<br>- f81803a_pme_init(dev);<br>-#ifdef F81803A_REGDUMP<br>- f81803a_pme_reg_dump(dev, "after");<br>-#endif<br>- break;<br>-<br>-<br>+ case F81803A_PME:<br>+ f81803a_pme_init(dev);<br>+ break;<br> }<br> <br> }<br> <br> static struct device_operations ops = {<br>- .read_resources = pnp_read_resources,<br>- .set_resources = pnp_set_resources,<br>- .enable_resources = pnp_enable_resources,<br>- .enable = pnp_alt_enable,<br>- .init = f81803a_init,<br>- .ops_pnp_mode = &pnp_conf_mode_8787_aa,<br>+ .read_resources = pnp_read_resources,<br>+ .set_resources = pnp_set_resources,<br>+ .enable_resources = pnp_enable_resources,<br>+ .enable = pnp_alt_enable,<br>+ .init = f81803a_init,<br>+ .ops_pnp_mode = &pnp_conf_mode_8787_aa,<br> };<br> <br> static struct pnp_info pnp_dev_info[] = {<br>@@ -155,6 +76,5 @@<br> }<br> <br> struct chip_operations superio_fintek_f81803a_ops = {<br>- CHIP_NAME("Fintek F81803A Super I/O")<br> .enable_dev = enable_dev<br> };<br></pre><p>To view, visit <a href="https://review.coreboot.org/21047">change 21047</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/21047"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Ib4b078a590ba27f698dad84d6bd6237c8331e60f </div>
<div style="display:none"> Gerrit-Change-Number: 21047 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: John E. Kabat <sljkrr@gmail.com> </div>
<div style="display:none"> Gerrit-Reviewer: John E. Kabat Jr. <john.kabat@scarletltd.com> </div>