[coreboot-gerrit] Change in coreboot[master]: AMD Padmelon Power Button Fix
John E. Kabat (Code Review)
gerrit at coreboot.org
Wed Aug 16 16:28:05 CEST 2017
Hello John E. Kabat Jr.,
I'd like you to do a code review. Please visit
https://review.coreboot.org/21045
to review the following change.
Change subject: AMD Padmelon Power Button Fix
......................................................................
AMD Padmelon Power Button Fix
This code allows the Padmelon power button to work properly.
Initialization of the F81803A was corrected and gpe.asl was modified
to use _l08 for the power button and reset thePSIN_FLAG inthe SIO.
Change-Id: I025be4d6bcc9de668681b59eb54dbcdbdd092bce
Signed-off-by: John Kabat <john.kabat at scarletltd.com>
---
M src/mainboard/amd/padmelon/acpi/gpe.asl
A src/mainboard/amd/padmelon/acpi/superio.asl
M src/mainboard/amd/padmelon/devicetree.cb
M src/mainboard/amd/padmelon/dsdt.asl
M src/superio/fintek/f81803a/Makefile.inc
A src/superio/fintek/f81803a/chip.h
M src/superio/fintek/f81803a/f81803a.h
A src/superio/fintek/f81803a/f81803a_pme.c
A src/superio/fintek/f81803a/fintek_internal.h
M src/superio/fintek/f81803a/superio.c
10 files changed, 439 insertions(+), 10 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/21045/1
diff --git a/src/mainboard/amd/padmelon/acpi/gpe.asl b/src/mainboard/amd/padmelon/acpi/gpe.asl
index 9a84698..ba8d878 100644
--- a/src/mainboard/amd/padmelon/acpi/gpe.asl
+++ b/src/mainboard/amd/padmelon/acpi/gpe.asl
@@ -17,13 +17,19 @@
/* General event 3 */
Method(_L03) {
- /* DBGO("\\_GPE\\_L00\n") */
- Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
+ /* DBGO("\\_GPE\\_L03\n") */
+ Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
}
- /* Legacy PM event */
+ /* Legacy PM event - Power Button */
Method(_L08) {
- /* DBGO("\\_GPE\\_L08\n") */
+ /* DBGO("\\_GPE\\_L08\n") */
+ \_SB.SIO0.CPSI() /* clear psin state in sio */
+ Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
}
/* Temp warning (TWarn) event */
@@ -34,7 +40,7 @@
/* USB controller PME# */
Method(_L0B) {
- /* DBGO("\\_GPE\\_L0B\n") */
+ /* DBGO("\\_GPE\\_L0B\n") */
Notify(\_SB.PCI0.UOH1, 0x02) /* NOTIFY_DEVICE_WAKE */
Notify(\_SB.PCI0.UOH2, 0x02) /* NOTIFY_DEVICE_WAKE */
Notify(\_SB.PCI0.UOH3, 0x02) /* NOTIFY_DEVICE_WAKE */
@@ -57,7 +63,7 @@
/* GPIO0 or GEvent8 event */
Method(_L18) {
- /* DBGO("\\_GPE\\_L18\n") */
+ /* DBGO("\\_GPE\\_L18\n") */
Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */
Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */
Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */
diff --git a/src/mainboard/amd/padmelon/acpi/superio.asl b/src/mainboard/amd/padmelon/acpi/superio.asl
new file mode 100644
index 0000000..5341f82
--- /dev/null
+++ b/src/mainboard/amd/padmelon/acpi/superio.asl
@@ -0,0 +1,191 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Christoph Grenz <christophg+cb at grenz-bonn.de>
+ * Copyright (C) 2013 secunet Security Networks AG
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/*
+ * Include this file into a mainboard's DSDT _SB device tree and it will
+ * expose the W83627DHG SuperIO and some of its functionality.
+ *
+ * It allows the change of IO ports, IRQs and DMA settings on logical
+ * devices, disabling and reenabling logical devices and controlling power
+ * saving mode on logical devices or the whole chip.
+ *
+ * LDN State
+ * 0x1 UARTA Implemented, partially tested
+ * 0x2 UARTB UART only, partially tested
+ * 0x4 HWM Resources, PM only
+ * 0x5 KBC Implemented, untested
+ * 0x6 GPIO6 Not implemented
+ * 0x7 WDT0&PLED Not implemented
+ * 0x9 GPIO2-5 Not implemented
+ * 0xa ACPI/PME/ERP Not implemented
+ *
+ * Controllable through preprocessor defines:
+ * SUPERIO_DEV Device identifier for this SIO (e.g. SIO0)
+ * SUPERIO_PNP_BASE I/o address of the first PnP configuration register
+ * F81803A_SHOW_UARTA If defined, UARTA will be exposed.
+ * F81803A_SHOW_UARTB If defined, UARTB will be exposed.
+ * F81803A_SHOW_KBC If defined, the KBC will be exposed.
+ * F81803A_SHOW_PS2M If defined, PS/2 mouse support will be exposed.
+ * F81803A_SHOW_HWMON If defined, the hardware monitor will be exposed.
+ * F81803A_SHOW_PME If defined, the PME/EARP/ACPI will be exposed.
+ */
+#undef SUPERIO_DEV
+#define SUPERIO_DEV SIO0
+#undef SUPERIO_CHIP_NAME
+#define SUPERIO_CHIP_NAME F81803A
+#define SUPERIO_PNP_BASE 0x4E
+#include <superio/acpi/pnp.asl>
+
+Device(SUPERIO_DEV) {
+ Name (_HID, EisaId("PNP0A05"))
+ Name (_STR, Unicode("Fintek F81803A Super I/O"))
+ Name (_UID, SUPERIO_UID(SUPERIO_DEV,))
+
+ /* Mutex for accesses to the configuration ports */
+ Mutex(CRMX, 1)
+
+ /* SuperIO configuration ports */
+ OperationRegion (CREG, SystemIO, SUPERIO_PNP_BASE, 0x02)
+ Field (CREG, ByteAcc, NoLock, Preserve)
+ {
+ PNP_ADDR_REG, 8,
+ PNP_DATA_REG, 8
+ }
+ IndexField (ADDR, DATA, ByteAcc, NoLock, Preserve)
+ {
+ Offset (0x07),
+ PNP_LOGICAL_DEVICE, 8, /* Logical device selector */
+
+
+ Offset (0x30),
+ PNP_DEVICE_ACTIVE, 1, /* Logical device activation */
+
+ Offset (0x60),
+ PNP_IO0_HIGH_BYTE, 8, /* First I/O port base - high byte */
+ PNP_IO0_LOW_BYTE, 8, /* First I/O port base - low byte */
+ Offset (0x62),
+ PNP_IO1_HIGH_BYTE, 8, /* Second I/O port base - high byte */
+ PNP_IO1_LOW_BYTE, 8, /* Second I/O port base - low byte */
+
+ Offset (0x70),
+ PNP_IRQ0, 8, /* First IRQ */
+
+ offset(0xFB),
+ APC5, 8, /* PME ACPI Control Register 5 */
+ }
+
+
+
+ /* PMx-- registers to get the addresses of the ACPI Registers */
+ IndexField(PNP_ADDR_REG, PNP_DATA_REG, ByteAcc, NoLock, Preserve)
+ {
+ Offset(0x60), /* AcpiPmEvBlk */
+ P1EB, 16, /* AcpiPmEvtBlk */
+ P1CB, 16, /* AcpiPm1CntBlk */
+ Offset(0xEE),
+ UPWS, 3,
+ }
+
+
+ /* AcpiPmEvtBlk registers*/
+ OperationRegion(P1E0, SystemIO, P1EB, 0x04)
+ Field(P1E0, ByteAcc, Nolock, Preserve)
+ {
+ Offset(0x02), /* Pm1Enable */
+ , 14,
+ PEWD, 1, /* bit 1: PciExpWakeDis*/
+ }
+
+
+ /* AcpiPm1CntBlk registers*/
+ OperationRegion(P1C0, SystemIO, P1CB, 0x04)
+ Field(P1C0, ByteAcc, Nolock, Preserve)
+ {
+ Offset(0x00), /* PmControl */
+ , 10,
+ P1ST, 3, /* Bits SlpTyp */
+ P1SE, 1, /* SlpTypEn*/
+ }
+
+ OperationRegion(APCx, SystemIO, APC5, 0x01)
+ Field(APCx, ByteAcc, Nolock, Preserve) /* bits in PME ACPI CONTROL Reg 5*/
+ {
+ Offset(0x00), /*Control Reg 5 */
+ , 7,
+ PSIN, 1, /* PSIN_FLAG */
+ }
+
+ /* routine to clear PSIN_FLAG in ACPI_CONTROL_REG_5 of SIO */
+ Method(CPSI, 0, Serialized)
+ {
+ /* DBG0("SIO CPSI")*/
+ ENTER_CONFIG_MODE(10)
+ Store(1, PSIN)
+ EXIT_CONFIG_MODE()
+ }
+
+
+
+ Method(_CRS)
+ {
+ /* Announce the used i/o ports to the OS */
+ Return (ResourceTemplate () {
+ IO (Decode16, SUPERIO_PNP_BASE, SUPERIO_PNP_BASE, 0x01, 0x02)
+ })
+ }
+
+
+
+ #undef PNP_ENTER_MAGIC_1ST
+ #undef PNP_ENTER_MAGIC_2ND
+ #undef PNP_ENTER_MAGIC_3RD
+ #undef PNP_ENTER_MAGIC_4TH
+ #undef PNP_EXIT_MAGIC_1ST
+ #undef PNP_EXIT_SPECIAL_REG
+ #undef PNP_EXIT_SPECIAL_VAL
+ #define PNP_ENTER_MAGIC_1ST 0x87
+ #define PNP_ENTER_MAGIC_2ND 0x87
+ #define PNP_EXIT_MAGIC_1ST 0xaa
+ #include <superio/acpi/pnp_config.asl>
+
+#ifdef F81803A_SHOW_UARTA
+ #undef SUPERIO_UART_LDN
+ #undef SUPERIO_UART_DDN
+ #undef SUPERIO_UART_PM_REG
+ #undef SUPERIO_UART_PM_VAL
+ #undef SUPERIO_UART_PM_LDN
+ #define SUPERIO_UART_LDN 1
+ #define SUPERIO_UART_PM_REG UAPW
+ #define SUPERIO_UART_PM_VAL 0
+ #define SUPERIO_UART_PM_LDN PNP_NO_LDN_CHANGE
+ #include <superio/acpi/pnp_uart.asl>
+#endif
+
+#ifdef F81803A_SHOW_UARTB
+ #undef SUPERIO_UART_LDN
+ #undef SUPERIO_UART_DDN
+ #undef SUPERIO_UART_PM_REG
+ #undef SUPERIO_UART_PM_VAL
+ #undef SUPERIO_UART_PM_LDN
+ #define SUPERIO_UART_LDN 2
+ #define SUPERIO_UART_PM_REG UBPW
+ #define SUPERIO_UART_PM_VAL 0
+ #define SUPERIO_UART_PM_LDN PNP_NO_LDN_CHANGE
+ #include <superio/acpi/pnp_uart.asl>
+#endif
+
+
+}
diff --git a/src/mainboard/amd/padmelon/devicetree.cb b/src/mainboard/amd/padmelon/devicetree.cb
index 1902311..f47cc70 100644
--- a/src/mainboard/amd/padmelon/devicetree.cb
+++ b/src/mainboard/amd/padmelon/devicetree.cb
@@ -54,7 +54,6 @@
end # SM
device pci 14.3 on # LPC 0x439d
chip superio/fintek/f81803a
- register "conf_key_mode" = "0x77"
device pnp 4e.1 on # COM1
io 0x60 = 0x3f8
irq 0x70 = 4
@@ -67,7 +66,7 @@
device pnp 4e.5 off end # KBC
device pnp 4e.6 off end # GPIO
device pnp 4e.7 off end # WDT
- device pnp 4e.a off end # PME
+ device pnp 4e.a on end # PME
end # f81803a
end # LPC
diff --git a/src/mainboard/amd/padmelon/dsdt.asl b/src/mainboard/amd/padmelon/dsdt.asl
index 2e6c96c..470ee26 100644
--- a/src/mainboard/amd/padmelon/dsdt.asl
+++ b/src/mainboard/amd/padmelon/dsdt.asl
@@ -34,7 +34,7 @@
/* PCI IRQ mapping for the Southbridge */
#include <southbridge/amd/pi/hudson/acpi/pcie.asl>
- /* Describe the processor tree (\_PR) */
+ /* Describe the processor tree (\_PR) */
#include <cpu/amd/pi/00660F01/acpi/cpu.asl>
/* Contains the supported sleep states for this chipset */
@@ -72,6 +72,9 @@
/* Describe the devices in the Southbridge */
#include "acpi/carrizo_fch.asl"
+ /* Describe the Fintek F81803A SIO */
+ #include "acpi/superio.asl"
+
} /* End \_SB scope */
/* Describe SMBUS for the Southbridge */
diff --git a/src/superio/fintek/f81803a/Makefile.inc b/src/superio/fintek/f81803a/Makefile.inc
index 9156bf9..372de05 100644
--- a/src/superio/fintek/f81803a/Makefile.inc
+++ b/src/superio/fintek/f81803a/Makefile.inc
@@ -15,3 +15,4 @@
##
ramstage-$(CONFIG_SUPERIO_FINTEK_F81803A) += superio.c
+ramstage-$(CONFIG_SUPERIO_FINTEK_F81803A) += f81803a_pme.c
diff --git a/src/superio/fintek/f81803a/chip.h b/src/superio/fintek/f81803a/chip.h
new file mode 100644
index 0000000..063f746
--- /dev/null
+++ b/src/superio/fintek/f81803a/chip.h
@@ -0,0 +1,63 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Edward O'Callaghan <eocallaghan at alterapraxis.com>
+ * Copyright (C) 2017 Nicola Corna <nicola at corna.info>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef SUPERIO_FINTEK_F81803A_CHIP_H
+#define SUPERIO_FINTEK_F81803A_CHIP_H
+
+#include <stdint.h>
+
+/* register in Fintek F81803A */
+#define LDN_REG 0x07
+
+/* Global Control Registers */
+#define CLOCK_SELECT_REG 0x26
+#define FUNC_PROG_SELECT (1<<3)
+#define CONFIG_PORT_SELECT_REG 0x27
+
+#define TSI_LEVEL_SELECT_REG 0x28 /* FUNC_PROG_SEL = 0 */
+#define TSI_PIN_SELECT_REG 0x28 /* FUNC_PROG_SEL = 1 */
+#define MULTI_FUNC_SEL_REG1 0x29
+#define MULTI_FUNC_SEL_REG2 0x2A
+#define MULTI_FUNC_SEL_REG3 0x2B
+#define MULTI_FUNC_SEL_REG4 0x2C
+#define WAKEUP_CONTROL_REG 0x2d
+
+/* LUN A - PMZE, ACPI, ERP */
+#define PME_DEVICE_ENABLE_REG 0x30
+#define PME_ENABLE (1<<0)
+#define PME_ERP_ENABLE_REG 0xE0
+#define ERP_ENABLE (1<<7)
+#define ERP_PME_EN (1<<1)
+#define ERP_PSOUT_EN (1<<0)
+#define PME_ERP_CONTROL_1_REG 0xE1
+#define PME_ERP_CONTROL_2_REG 0xE2
+#define PME_ERP_PSIN_DEBOUNCE_REG 0xE3
+#define PME_ERP_WAKEUP_ENABLE_REG 0xE8
+#define PME_ERP_MODE_SELECT_REG 0xEC
+#define PME_EVENT_ENABLE_1_REG 0xF0
+#define PME_EVENT_STATUS_1_REG 0xF1
+#define PME_EVENT_ENABLE_2_REG 0xF2
+#define PME_EVENT_STATUS_2_REG 0xF3
+#define PME_ACPI_CONTROL_1_REG 0xF4
+#define PME_ACPI_CONTROL_2_REG 0xF5
+#define PME_ACPI_CONTROL_3_REG 0xF6
+#define PME_ACPI_CONTROL_4_REG 0xF7
+#define PME_ACPI_CONTROL_5_REG 0xFB
+#define PME_ACPI_CONTROL_6_REG 0xFC
+
+
+#endif /* SUPERIO_FINTEK_F81803A_CHIP_H */
diff --git a/src/superio/fintek/f81803a/f81803a.h b/src/superio/fintek/f81803a/f81803a.h
index ed78cab..9e2055c 100644
--- a/src/superio/fintek/f81803a/f81803a.h
+++ b/src/superio/fintek/f81803a/f81803a.h
@@ -18,6 +18,7 @@
* Datasheet:
* - Name: F81803A
*/
+
#ifndef SUPERIO_FINTEK_F81803_H
#define SUPERIO_FINTEK_F81803_H
@@ -31,3 +32,5 @@
#define F81803A_PME 0x0a /* Power Management Events (PME) */
#endif /* SUPERIO_FINTEK_F81803_H */
+#include "fintek_internal.h"
+
diff --git a/src/superio/fintek/f81803a/f81803a_pme.c b/src/superio/fintek/f81803a/f81803a_pme.c
new file mode 100644
index 0000000..2223212
--- /dev/null
+++ b/src/superio/fintek/f81803a/f81803a_pme.c
@@ -0,0 +1,39 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Edward O'Callaghan <eocallaghan at alterapraxis.com>
+ * Copyright (C) 2017 Nicola Corna <nicola at corna.info>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/io.h>
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pnp.h>
+#include "f81803a.h"
+
+
+
+void f81803a_pme_init(struct device *dev)
+{
+
+ printk(BIOS_INFO, "F81803A PME: Init.\n");
+
+ pnp_enter_conf_mode(dev);
+ pnp_write_config(dev, LDN_REG, F81803A_PME);
+
+ /* enable ERP function*/
+ /* also set PSIN to generate PSOUT*/
+ pnp_write_config(dev, PME_ERP_ENABLE_REG,ERP_ENABLE | ERP_PSOUT_EN);
+
+ pnp_exit_conf_mode(dev);
+}
diff --git a/src/superio/fintek/f81803a/fintek_internal.h b/src/superio/fintek/f81803a/fintek_internal.h
new file mode 100644
index 0000000..5b8d275
--- /dev/null
+++ b/src/superio/fintek/f81803a/fintek_internal.h
@@ -0,0 +1,32 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Edward O'Callaghan <eocallaghan at alterapraxis.com>
+ * Copyright (C) 2017 Nicola Corna <nicola at corna.info>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef SUPERIO_FINTEK_F81803A_INTERNAL_H
+#define SUPERIO_FINTEK_F81803A_INTERNAL_H
+
+#include <arch/io.h>
+#include <device/pnp.h>
+#include "chip.h"
+
+struct f81803a_reg_tab
+{
+ const char *reg_name;
+ uint8_t reg;
+};
+void f81803a_pme_init(struct device *dev);
+void f81803a_reg_dump(struct device *dev, struct f81803a_reg_tab *tab);
+#endif /* SUPERIO_FINTEK_F81803A_INTERNAL_H */
diff --git a/src/superio/fintek/f81803a/superio.c b/src/superio/fintek/f81803a/superio.c
index c5504c1..3f5636a 100644
--- a/src/superio/fintek/f81803a/superio.c
+++ b/src/superio/fintek/f81803a/superio.c
@@ -23,8 +23,87 @@
#include <pc80/keyboard.h>
#include "f81803a.h"
+#ifdef F81803A_REGDUMP
+/* for Debug */
+static struct f81803a_reg_tab f81803a_pme_regs1[] = {
+
+ { "CLOCK_SELECT_REG", CLOCK_SELECT_REG },
+ { "CONFIG_PORT_SELECT_REG", CONFIG_PORT_SELECT_REG },
+ { "TSI_PIN_SELECT_REG", TSI_PIN_SELECT_REG },
+ { NULL, 0 }
+};
+
+
+static struct f81803a_reg_tab f81803a_pme_regs2[] = {
+ { "TSI_LEVEL_SELECT_REG", TSI_LEVEL_SELECT_REG },
+ { "MULTI_FUNC_SEL_REG1", MULTI_FUNC_SEL_REG1 },
+ { "MULTI_FUNC_SEL_REG2", MULTI_FUNC_SEL_REG2 },
+ { "MULTI_FUNC_SEL_REG3", MULTI_FUNC_SEL_REG3 },
+ { "MULTI_FUNC_SEL_REG4", MULTI_FUNC_SEL_REG4 },
+ { "WAKEUP_CONTROL_REG", WAKEUP_CONTROL_REG },
+ { "PME_DEVICE_ENABLE_REG", PME_DEVICE_ENABLE_REG },
+ { "PME_ERP_ENABLE_REG", PME_ERP_ENABLE_REG },
+ { "PME_ERP_CONTROL_1_REG", PME_ERP_CONTROL_1_REG },
+ { "PME_ERP_CONTROL_2_REG", PME_ERP_CONTROL_2_REG },
+ { "PME_ERP_PSIN_DEBOUNCE_REG", PME_ERP_PSIN_DEBOUNCE_REG },
+ { "PME_ERP_WAKEUP_ENABLE_REG", PME_ERP_WAKEUP_ENABLE_REG },
+ { "PME_EVENT_ENABLE_1_REG", PME_EVENT_ENABLE_1_REG },
+ { "PME_EVENT_ENABLE_2_REG", PME_EVENT_ENABLE_2_REG },
+ { "PME_ACPI_CONTROL_1_REG", PME_ACPI_CONTROL_1_REG },
+ { "PME_ACPI_CONTROL_2_REG", PME_ACPI_CONTROL_2_REG },
+ { "PME_ACPI_CONTROL_3_REG", PME_ACPI_CONTROL_3_REG },
+ { "PME_ACPI_CONTROL_4_REG", PME_ACPI_CONTROL_4_REG },
+ { "PME_ACPI_CONTROL_5_REG", PME_ACPI_CONTROL_5_REG },
+ { "PME_ACPI_CONTROL_6_REG", PME_ACPI_CONTROL_6_REG },
+ { NULL, 0 }
+};
+
+void f81803a_reg_dump(struct device *dev, struct f81803a_reg_tab *tab)
+{
+ uint8_t val;
+ for (; tab->reg_name; tab++)
+ {
+ val = pnp_read_config(dev, tab->reg);
+ printk(BIOS_INFO, " %02X %s %02X\n", tab->reg, tab->reg_name, val & 0xff);
+ }
+
+}
+static void f81803a_pme_reg_dump(struct device *dev, const char *s)
+{
+ uint8_t save_clock_select;
+ printk(BIOS_INFO, "\nF81803A PME: Regs %s\n", s);
+ pnp_enter_conf_mode(dev);
+ pnp_write_config(dev, LDN_REG, F81803A_PME);
+ /*
+ * this is done with two tables as FUNC_PROG_SEL in CLOCK_SELECT_REG
+ * is used as a bank select register for the TSI registers index 28
+ * We assume that FUNC_PROG_SELECT is 0 for now
+ *
+ * Note the actual writeup for FUNC_PROG_SEL on page 52 say:
+ * "Index 0x29, 0x2B and 0x2C bank select register"
+ * However this is not the case and only reg 28 appears to be affected
+ * TODO: Confirm this
+ */
+
+ /* read CLOCK_SELECT_REGISTER and save it */
+ save_clock_select = pnp_read_config(dev, CLOCK_SELECT_REG);
+ /* set FUNC_PROG_SELECT so we read TSI_PIN_SELECT*/
+ pnp_write_config(dev, CLOCK_SELECT_REG, save_clock_select | FUNC_PROG_SELECT);
+ f81803a_reg_dump(dev, f81803a_pme_regs1);
+
+ /* now set it back to 0 and read the rest*/
+
+ pnp_write_config(dev, CLOCK_SELECT_REG, save_clock_select);
+ f81803a_reg_dump(dev, f81803a_pme_regs2);
+
+ pnp_exit_conf_mode(dev);
+ printk(BIOS_INFO, "\nF81803A PME: Regs Done %s\n", s);
+}
+#endif
static void f81803a_init(struct device *dev)
{
+
+ printk(BIOS_INFO, "F81803A_INIT.\n");
if (!dev->enabled)
return;
@@ -34,7 +113,19 @@
case F81803A_KBC:
pc_keyboard_init(NO_AUX_DEVICE);
break;
+ case F81803A_PME:
+#ifdef F81803A_REGDUMP
+ f81803a_pme_reg_dump(dev,"before");
+#endif
+ f81803a_pme_init(dev);
+#ifdef F81803A_REGDUMP
+ f81803a_pme_reg_dump(dev, "after");
+#endif
+ break;
+
+
}
+
}
static struct device_operations ops = {
@@ -53,12 +144,13 @@
{ &ops, F81803A_HWM, PNP_IO0 | PNP_IRQ0, 0xff8, },
{ &ops, F81803A_KBC, PNP_IO0 | PNP_IRQ0 | PNP_IRQ1, 0x07ff, },
{ &ops, F81803A_GPIO, PNP_IO0 | PNP_IRQ0, 0x7f8, },
- { &ops, F81803A_WDT, PNP_IO0, 0x7f8 },
+ //{ &ops, F81803A_WDT, PNP_IO0, 0x7f8 },
{ &ops, F81803A_PME, },
};
static void enable_dev(struct device *dev)
{
+ printk(BIOS_INFO, "F81803A : enable_dev\n");
pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info);
}
--
To view, visit https://review.coreboot.org/21045
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I025be4d6bcc9de668681b59eb54dbcdbdd092bce
Gerrit-Change-Number: 21045
Gerrit-PatchSet: 1
Gerrit-Owner: John E. Kabat <sljkrr at gmail.com>
Gerrit-Reviewer: John E. Kabat Jr. <john.kabat at scarletltd.com>
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