<p>John E. Kabat would like John E. Kabat Jr. to <strong>review</strong> this change.</p><p><a href="https://review.coreboot.org/21045">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">AMD Padmelon Power Button Fix<br><br>This code allows the Padmelon power button to work properly.<br>Initialization of the F81803A was corrected and gpe.asl was modified<br>to use _l08 for the power button and reset thePSIN_FLAG inthe SIO.<br><br>Change-Id: I025be4d6bcc9de668681b59eb54dbcdbdd092bce<br>Signed-off-by: John Kabat <john.kabat@scarletltd.com><br>---<br>M src/mainboard/amd/padmelon/acpi/gpe.asl<br>A src/mainboard/amd/padmelon/acpi/superio.asl<br>M src/mainboard/amd/padmelon/devicetree.cb<br>M src/mainboard/amd/padmelon/dsdt.asl<br>M src/superio/fintek/f81803a/Makefile.inc<br>A src/superio/fintek/f81803a/chip.h<br>M src/superio/fintek/f81803a/f81803a.h<br>A src/superio/fintek/f81803a/f81803a_pme.c<br>A src/superio/fintek/f81803a/fintek_internal.h<br>M src/superio/fintek/f81803a/superio.c<br>10 files changed, 439 insertions(+), 10 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/21045/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/mainboard/amd/padmelon/acpi/gpe.asl b/src/mainboard/amd/padmelon/acpi/gpe.asl<br>index 9a84698..ba8d878 100644<br>--- a/src/mainboard/amd/padmelon/acpi/gpe.asl<br>+++ b/src/mainboard/amd/padmelon/acpi/gpe.asl<br>@@ -17,13 +17,19 @@<br> <br> /* General event 3 */<br> Method(_L03) {<br>- /* DBGO("\\_GPE\\_L00\n") */<br>- Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */<br>+ /* DBGO("\\_GPE\\_L03\n") */<br>+ Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */<br> }<br> <br>- /* Legacy PM event */<br>+ /* Legacy PM event - Power Button */<br> Method(_L08) {<br>- /* DBGO("\\_GPE\\_L08\n") */<br>+ /* DBGO("\\_GPE\\_L08\n") */<br>+ \_SB.SIO0.CPSI() /* clear psin state in sio */<br>+ Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */<br>+ Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */<br>+ Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */<br>+ Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */<br>+ Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */<br> }<br> <br> /* Temp warning (TWarn) event */<br>@@ -34,7 +40,7 @@<br> <br> /* USB controller PME# */<br> Method(_L0B) {<br>- /* DBGO("\\_GPE\\_L0B\n") */<br>+ /* DBGO("\\_GPE\\_L0B\n") */<br> Notify(\_SB.PCI0.UOH1, 0x02) /* NOTIFY_DEVICE_WAKE */<br> Notify(\_SB.PCI0.UOH2, 0x02) /* NOTIFY_DEVICE_WAKE */<br> Notify(\_SB.PCI0.UOH3, 0x02) /* NOTIFY_DEVICE_WAKE */<br>@@ -57,7 +63,7 @@<br> <br> /* GPIO0 or GEvent8 event */<br> Method(_L18) {<br>- /* DBGO("\\_GPE\\_L18\n") */<br>+ /* DBGO("\\_GPE\\_L18\n") */<br> Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */<br> Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */<br> Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */<br>diff --git a/src/mainboard/amd/padmelon/acpi/superio.asl b/src/mainboard/amd/padmelon/acpi/superio.asl<br>new file mode 100644<br>index 0000000..5341f82<br>--- /dev/null<br>+++ b/src/mainboard/amd/padmelon/acpi/superio.asl<br>@@ -0,0 +1,191 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright (C) 2011 Christoph Grenz <christophg+cb@grenz-bonn.de><br>+ * Copyright (C) 2013 secunet Security Networks AG<br>+ *<br>+ * This program is free software; you can redistribute it and/or modify<br>+ * it under the terms of the GNU General Public License as published by<br>+ * the Free Software Foundation; version 2 of the License.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ */<br>+<br>+/*<br>+ * Include this file into a mainboard's DSDT _SB device tree and it will<br>+ * expose the W83627DHG SuperIO and some of its functionality.<br>+ *<br>+ * It allows the change of IO ports, IRQs and DMA settings on logical<br>+ * devices, disabling and reenabling logical devices and controlling power<br>+ * saving mode on logical devices or the whole chip.<br>+ *<br>+ * LDN State<br>+ * 0x1 UARTA Implemented, partially tested<br>+ * 0x2 UARTB UART only, partially tested<br>+ * 0x4 HWM Resources, PM only<br>+ * 0x5 KBC Implemented, untested<br>+ * 0x6 GPIO6 Not implemented<br>+ * 0x7 WDT0&PLED Not implemented<br>+ * 0x9 GPIO2-5 Not implemented<br>+ * 0xa ACPI/PME/ERP Not implemented<br>+ *<br>+ * Controllable through preprocessor defines:<br>+ * SUPERIO_DEV Device identifier for this SIO (e.g. SIO0)<br>+ * SUPERIO_PNP_BASE I/o address of the first PnP configuration register<br>+ * F81803A_SHOW_UARTA If defined, UARTA will be exposed.<br>+ * F81803A_SHOW_UARTB If defined, UARTB will be exposed.<br>+ * F81803A_SHOW_KBC If defined, the KBC will be exposed.<br>+ * F81803A_SHOW_PS2M If defined, PS/2 mouse support will be exposed.<br>+ * F81803A_SHOW_HWMON If defined, the hardware monitor will be exposed.<br>+ * F81803A_SHOW_PME If defined, the PME/EARP/ACPI will be exposed.<br>+ */<br>+#undef SUPERIO_DEV<br>+#define SUPERIO_DEV SIO0<br>+#undef SUPERIO_CHIP_NAME<br>+#define SUPERIO_CHIP_NAME F81803A<br>+#define SUPERIO_PNP_BASE 0x4E<br>+#include <superio/acpi/pnp.asl><br>+<br>+Device(SUPERIO_DEV) {<br>+ Name (_HID, EisaId("PNP0A05"))<br>+ Name (_STR, Unicode("Fintek F81803A Super I/O"))<br>+ Name (_UID, SUPERIO_UID(SUPERIO_DEV,))<br>+<br>+ /* Mutex for accesses to the configuration ports */<br>+ Mutex(CRMX, 1)<br>+<br>+ /* SuperIO configuration ports */<br>+ OperationRegion (CREG, SystemIO, SUPERIO_PNP_BASE, 0x02)<br>+ Field (CREG, ByteAcc, NoLock, Preserve)<br>+ {<br>+ PNP_ADDR_REG, 8,<br>+ PNP_DATA_REG, 8<br>+ }<br>+ IndexField (ADDR, DATA, ByteAcc, NoLock, Preserve)<br>+ {<br>+ Offset (0x07),<br>+ PNP_LOGICAL_DEVICE, 8, /* Logical device selector */<br>+<br>+<br>+ Offset (0x30),<br>+ PNP_DEVICE_ACTIVE, 1, /* Logical device activation */<br>+<br>+ Offset (0x60),<br>+ PNP_IO0_HIGH_BYTE, 8, /* First I/O port base - high byte */<br>+ PNP_IO0_LOW_BYTE, 8, /* First I/O port base - low byte */<br>+ Offset (0x62),<br>+ PNP_IO1_HIGH_BYTE, 8, /* Second I/O port base - high byte */<br>+ PNP_IO1_LOW_BYTE, 8, /* Second I/O port base - low byte */<br>+<br>+ Offset (0x70),<br>+ PNP_IRQ0, 8, /* First IRQ */<br>+<br>+ offset(0xFB),<br>+ APC5, 8, /* PME ACPI Control Register 5 */<br>+ }<br>+<br>+<br>+<br>+ /* PMx-- registers to get the addresses of the ACPI Registers */<br>+ IndexField(PNP_ADDR_REG, PNP_DATA_REG, ByteAcc, NoLock, Preserve)<br>+ {<br>+ Offset(0x60), /* AcpiPmEvBlk */<br>+ P1EB, 16, /* AcpiPmEvtBlk */<br>+ P1CB, 16, /* AcpiPm1CntBlk */<br>+ Offset(0xEE),<br>+ UPWS, 3,<br>+ }<br>+<br>+<br>+ /* AcpiPmEvtBlk registers*/<br>+ OperationRegion(P1E0, SystemIO, P1EB, 0x04)<br>+ Field(P1E0, ByteAcc, Nolock, Preserve)<br>+ {<br>+ Offset(0x02), /* Pm1Enable */<br>+ , 14,<br>+ PEWD, 1, /* bit 1: PciExpWakeDis*/<br>+ }<br>+<br>+<br>+ /* AcpiPm1CntBlk registers*/<br>+ OperationRegion(P1C0, SystemIO, P1CB, 0x04)<br>+ Field(P1C0, ByteAcc, Nolock, Preserve)<br>+ {<br>+ Offset(0x00), /* PmControl */<br>+ , 10,<br>+ P1ST, 3, /* Bits SlpTyp */<br>+ P1SE, 1, /* SlpTypEn*/<br>+ }<br>+<br>+ OperationRegion(APCx, SystemIO, APC5, 0x01)<br>+ Field(APCx, ByteAcc, Nolock, Preserve) /* bits in PME ACPI CONTROL Reg 5*/<br>+ {<br>+ Offset(0x00), /*Control Reg 5 */<br>+ , 7,<br>+ PSIN, 1, /* PSIN_FLAG */<br>+ }<br>+ <br>+ /* routine to clear PSIN_FLAG in ACPI_CONTROL_REG_5 of SIO */<br>+ Method(CPSI, 0, Serialized)<br>+ {<br>+ /* DBG0("SIO CPSI")*/<br>+ ENTER_CONFIG_MODE(10)<br>+ Store(1, PSIN)<br>+ EXIT_CONFIG_MODE()<br>+ }<br>+<br>+<br>+ <br>+ Method(_CRS)<br>+ {<br>+ /* Announce the used i/o ports to the OS */<br>+ Return (ResourceTemplate () {<br>+ IO (Decode16, SUPERIO_PNP_BASE, SUPERIO_PNP_BASE, 0x01, 0x02)<br>+ })<br>+ }<br>+<br>+<br>+<br>+ #undef PNP_ENTER_MAGIC_1ST<br>+ #undef PNP_ENTER_MAGIC_2ND<br>+ #undef PNP_ENTER_MAGIC_3RD<br>+ #undef PNP_ENTER_MAGIC_4TH<br>+ #undef PNP_EXIT_MAGIC_1ST<br>+ #undef PNP_EXIT_SPECIAL_REG<br>+ #undef PNP_EXIT_SPECIAL_VAL<br>+ #define PNP_ENTER_MAGIC_1ST 0x87<br>+ #define PNP_ENTER_MAGIC_2ND 0x87<br>+ #define PNP_EXIT_MAGIC_1ST 0xaa<br>+ #include <superio/acpi/pnp_config.asl><br>+<br>+#ifdef F81803A_SHOW_UARTA<br>+ #undef SUPERIO_UART_LDN<br>+ #undef SUPERIO_UART_DDN<br>+ #undef SUPERIO_UART_PM_REG<br>+ #undef SUPERIO_UART_PM_VAL<br>+ #undef SUPERIO_UART_PM_LDN<br>+ #define SUPERIO_UART_LDN 1<br>+ #define SUPERIO_UART_PM_REG UAPW<br>+ #define SUPERIO_UART_PM_VAL 0<br>+ #define SUPERIO_UART_PM_LDN PNP_NO_LDN_CHANGE<br>+ #include <superio/acpi/pnp_uart.asl><br>+#endif<br>+<br>+#ifdef F81803A_SHOW_UARTB<br>+ #undef SUPERIO_UART_LDN<br>+ #undef SUPERIO_UART_DDN<br>+ #undef SUPERIO_UART_PM_REG<br>+ #undef SUPERIO_UART_PM_VAL<br>+ #undef SUPERIO_UART_PM_LDN<br>+ #define SUPERIO_UART_LDN 2<br>+ #define SUPERIO_UART_PM_REG UBPW<br>+ #define SUPERIO_UART_PM_VAL 0<br>+ #define SUPERIO_UART_PM_LDN PNP_NO_LDN_CHANGE<br>+ #include <superio/acpi/pnp_uart.asl><br>+#endif<br>+<br>+<br>+}<br>diff --git a/src/mainboard/amd/padmelon/devicetree.cb b/src/mainboard/amd/padmelon/devicetree.cb<br>index 1902311..f47cc70 100644<br>--- a/src/mainboard/amd/padmelon/devicetree.cb<br>+++ b/src/mainboard/amd/padmelon/devicetree.cb<br>@@ -54,7 +54,6 @@<br> end # SM<br> device pci 14.3 on # LPC 0x439d<br> chip superio/fintek/f81803a<br>- register "conf_key_mode" = "0x77"<br> device pnp 4e.1 on # COM1<br> io 0x60 = 0x3f8<br> irq 0x70 = 4<br>@@ -67,7 +66,7 @@<br> device pnp 4e.5 off end # KBC<br> device pnp 4e.6 off end # GPIO<br> device pnp 4e.7 off end # WDT<br>- device pnp 4e.a off end # PME<br>+ device pnp 4e.a on end # PME<br> <br> end # f81803a<br> end # LPC<br>diff --git a/src/mainboard/amd/padmelon/dsdt.asl b/src/mainboard/amd/padmelon/dsdt.asl<br>index 2e6c96c..470ee26 100644<br>--- a/src/mainboard/amd/padmelon/dsdt.asl<br>+++ b/src/mainboard/amd/padmelon/dsdt.asl<br>@@ -34,7 +34,7 @@<br> /* PCI IRQ mapping for the Southbridge */<br> #include <southbridge/amd/pi/hudson/acpi/pcie.asl><br> <br>- /* Describe the processor tree (\_PR) */<br>+ /* Describe the processor tree (\_PR) */<br> #include <cpu/amd/pi/00660F01/acpi/cpu.asl><br> <br> /* Contains the supported sleep states for this chipset */<br>@@ -72,6 +72,9 @@<br> /* Describe the devices in the Southbridge */<br> #include "acpi/carrizo_fch.asl"<br> <br>+ /* Describe the Fintek F81803A SIO */<br>+ #include "acpi/superio.asl"<br>+<br> } /* End \_SB scope */<br> <br> /* Describe SMBUS for the Southbridge */<br>diff --git a/src/superio/fintek/f81803a/Makefile.inc b/src/superio/fintek/f81803a/Makefile.inc<br>index 9156bf9..372de05 100644<br>--- a/src/superio/fintek/f81803a/Makefile.inc<br>+++ b/src/superio/fintek/f81803a/Makefile.inc<br>@@ -15,3 +15,4 @@<br> ##<br> <br> ramstage-$(CONFIG_SUPERIO_FINTEK_F81803A) += superio.c<br>+ramstage-$(CONFIG_SUPERIO_FINTEK_F81803A) += f81803a_pme.c<br>diff --git a/src/superio/fintek/f81803a/chip.h b/src/superio/fintek/f81803a/chip.h<br>new file mode 100644<br>index 0000000..063f746<br>--- /dev/null<br>+++ b/src/superio/fintek/f81803a/chip.h<br>@@ -0,0 +1,63 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright (C) 2014 Edward O'Callaghan <eocallaghan@alterapraxis.com><br>+ * Copyright (C) 2017 Nicola Corna <nicola@corna.info><br>+ *<br>+ * This program is free software; you can redistribute it and/or modify<br>+ * it under the terms of the GNU General Public License as published by<br>+ * the Free Software Foundation; either version 2 of the License, or<br>+ * (at your option) any later version.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ */<br>+<br>+#ifndef SUPERIO_FINTEK_F81803A_CHIP_H<br>+#define SUPERIO_FINTEK_F81803A_CHIP_H<br>+<br>+#include <stdint.h><br>+<br>+/* register in Fintek F81803A */<br>+#define LDN_REG 0x07<br>+<br>+/* Global Control Registers */<br>+#define CLOCK_SELECT_REG 0x26<br>+#define FUNC_PROG_SELECT (1<<3)<br>+#define CONFIG_PORT_SELECT_REG 0x27<br>+<br>+#define TSI_LEVEL_SELECT_REG 0x28 /* FUNC_PROG_SEL = 0 */<br>+#define TSI_PIN_SELECT_REG 0x28 /* FUNC_PROG_SEL = 1 */<br>+#define MULTI_FUNC_SEL_REG1 0x29<br>+#define MULTI_FUNC_SEL_REG2 0x2A<br>+#define MULTI_FUNC_SEL_REG3 0x2B<br>+#define MULTI_FUNC_SEL_REG4 0x2C<br>+#define WAKEUP_CONTROL_REG 0x2d<br>+<br>+/* LUN A - PMZE, ACPI, ERP */<br>+#define PME_DEVICE_ENABLE_REG 0x30<br>+#define PME_ENABLE (1<<0)<br>+#define PME_ERP_ENABLE_REG 0xE0<br>+#define ERP_ENABLE (1<<7)<br>+#define ERP_PME_EN (1<<1)<br>+#define ERP_PSOUT_EN (1<<0)<br>+#define PME_ERP_CONTROL_1_REG 0xE1<br>+#define PME_ERP_CONTROL_2_REG 0xE2<br>+#define PME_ERP_PSIN_DEBOUNCE_REG 0xE3<br>+#define PME_ERP_WAKEUP_ENABLE_REG 0xE8<br>+#define PME_ERP_MODE_SELECT_REG 0xEC<br>+#define PME_EVENT_ENABLE_1_REG 0xF0<br>+#define PME_EVENT_STATUS_1_REG 0xF1<br>+#define PME_EVENT_ENABLE_2_REG 0xF2<br>+#define PME_EVENT_STATUS_2_REG 0xF3<br>+#define PME_ACPI_CONTROL_1_REG 0xF4<br>+#define PME_ACPI_CONTROL_2_REG 0xF5<br>+#define PME_ACPI_CONTROL_3_REG 0xF6<br>+#define PME_ACPI_CONTROL_4_REG 0xF7<br>+#define PME_ACPI_CONTROL_5_REG 0xFB<br>+#define PME_ACPI_CONTROL_6_REG 0xFC<br>+<br>+<br>+#endif /* SUPERIO_FINTEK_F81803A_CHIP_H */<br>diff --git a/src/superio/fintek/f81803a/f81803a.h b/src/superio/fintek/f81803a/f81803a.h<br>index ed78cab..9e2055c 100644<br>--- a/src/superio/fintek/f81803a/f81803a.h<br>+++ b/src/superio/fintek/f81803a/f81803a.h<br>@@ -18,6 +18,7 @@<br> * Datasheet:<br> * - Name: F81803A<br> */<br>+<br> #ifndef SUPERIO_FINTEK_F81803_H<br> #define SUPERIO_FINTEK_F81803_H<br> <br>@@ -31,3 +32,5 @@<br> #define F81803A_PME 0x0a /* Power Management Events (PME) */<br> <br> #endif /* SUPERIO_FINTEK_F81803_H */<br>+#include "fintek_internal.h"<br>+<br>diff --git a/src/superio/fintek/f81803a/f81803a_pme.c b/src/superio/fintek/f81803a/f81803a_pme.c<br>new file mode 100644<br>index 0000000..2223212<br>--- /dev/null<br>+++ b/src/superio/fintek/f81803a/f81803a_pme.c<br>@@ -0,0 +1,39 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright (C) 2014 Edward O'Callaghan <eocallaghan@alterapraxis.com><br>+ * Copyright (C) 2017 Nicola Corna <nicola@corna.info><br>+ *<br>+ * This program is free software; you can redistribute it and/or modify<br>+ * it under the terms of the GNU General Public License as published by<br>+ * the Free Software Foundation; either version 2 of the License, or<br>+ * (at your option) any later version.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ */<br>+<br>+#include <arch/io.h><br>+#include <console/console.h><br>+#include <device/device.h><br>+#include <device/pnp.h><br>+#include "f81803a.h"<br>+<br>+<br>+<br>+void f81803a_pme_init(struct device *dev)<br>+{<br>+<br>+ printk(BIOS_INFO, "F81803A PME: Init.\n");<br>+<br>+ pnp_enter_conf_mode(dev);<br>+ pnp_write_config(dev, LDN_REG, F81803A_PME);<br>+<br>+ /* enable ERP function*/<br>+ /* also set PSIN to generate PSOUT*/<br>+ pnp_write_config(dev, PME_ERP_ENABLE_REG,ERP_ENABLE | ERP_PSOUT_EN);<br>+<br>+ pnp_exit_conf_mode(dev);<br>+}<br>diff --git a/src/superio/fintek/f81803a/fintek_internal.h b/src/superio/fintek/f81803a/fintek_internal.h<br>new file mode 100644<br>index 0000000..5b8d275<br>--- /dev/null<br>+++ b/src/superio/fintek/f81803a/fintek_internal.h<br>@@ -0,0 +1,32 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright (C) 2014 Edward O'Callaghan <eocallaghan@alterapraxis.com><br>+ * Copyright (C) 2017 Nicola Corna <nicola@corna.info><br>+ *<br>+ * This program is free software; you can redistribute it and/or modify<br>+ * it under the terms of the GNU General Public License as published by<br>+ * the Free Software Foundation; either version 2 of the License, or<br>+ * (at your option) any later version.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ */<br>+<br>+#ifndef SUPERIO_FINTEK_F81803A_INTERNAL_H<br>+#define SUPERIO_FINTEK_F81803A_INTERNAL_H<br>+<br>+#include <arch/io.h><br>+#include <device/pnp.h><br>+#include "chip.h"<br>+<br>+struct f81803a_reg_tab<br>+{<br>+ const char *reg_name;<br>+ uint8_t reg;<br>+};<br>+void f81803a_pme_init(struct device *dev);<br>+void f81803a_reg_dump(struct device *dev, struct f81803a_reg_tab *tab);<br>+#endif /* SUPERIO_FINTEK_F81803A_INTERNAL_H */<br>diff --git a/src/superio/fintek/f81803a/superio.c b/src/superio/fintek/f81803a/superio.c<br>index c5504c1..3f5636a 100644<br>--- a/src/superio/fintek/f81803a/superio.c<br>+++ b/src/superio/fintek/f81803a/superio.c<br>@@ -23,8 +23,87 @@<br> #include <pc80/keyboard.h><br> #include "f81803a.h"<br> <br>+#ifdef F81803A_REGDUMP<br>+/* for Debug */<br>+static struct f81803a_reg_tab f81803a_pme_regs1[] = {<br>+<br>+ { "CLOCK_SELECT_REG", CLOCK_SELECT_REG },<br>+ { "CONFIG_PORT_SELECT_REG", CONFIG_PORT_SELECT_REG },<br>+ { "TSI_PIN_SELECT_REG", TSI_PIN_SELECT_REG },<br>+ { NULL, 0 }<br>+};<br>+<br>+<br>+static struct f81803a_reg_tab f81803a_pme_regs2[] = {<br>+ { "TSI_LEVEL_SELECT_REG", TSI_LEVEL_SELECT_REG },<br>+ { "MULTI_FUNC_SEL_REG1", MULTI_FUNC_SEL_REG1 },<br>+ { "MULTI_FUNC_SEL_REG2", MULTI_FUNC_SEL_REG2 },<br>+ { "MULTI_FUNC_SEL_REG3", MULTI_FUNC_SEL_REG3 },<br>+ { "MULTI_FUNC_SEL_REG4", MULTI_FUNC_SEL_REG4 },<br>+ { "WAKEUP_CONTROL_REG", WAKEUP_CONTROL_REG },<br>+ { "PME_DEVICE_ENABLE_REG", PME_DEVICE_ENABLE_REG },<br>+ { "PME_ERP_ENABLE_REG", PME_ERP_ENABLE_REG },<br>+ { "PME_ERP_CONTROL_1_REG", PME_ERP_CONTROL_1_REG },<br>+ { "PME_ERP_CONTROL_2_REG", PME_ERP_CONTROL_2_REG },<br>+ { "PME_ERP_PSIN_DEBOUNCE_REG", PME_ERP_PSIN_DEBOUNCE_REG },<br>+ { "PME_ERP_WAKEUP_ENABLE_REG", PME_ERP_WAKEUP_ENABLE_REG },<br>+ { "PME_EVENT_ENABLE_1_REG", PME_EVENT_ENABLE_1_REG },<br>+ { "PME_EVENT_ENABLE_2_REG", PME_EVENT_ENABLE_2_REG },<br>+ { "PME_ACPI_CONTROL_1_REG", PME_ACPI_CONTROL_1_REG },<br>+ { "PME_ACPI_CONTROL_2_REG", PME_ACPI_CONTROL_2_REG },<br>+ { "PME_ACPI_CONTROL_3_REG", PME_ACPI_CONTROL_3_REG },<br>+ { "PME_ACPI_CONTROL_4_REG", PME_ACPI_CONTROL_4_REG },<br>+ { "PME_ACPI_CONTROL_5_REG", PME_ACPI_CONTROL_5_REG },<br>+ { "PME_ACPI_CONTROL_6_REG", PME_ACPI_CONTROL_6_REG },<br>+ { NULL, 0 }<br>+};<br>+<br>+void f81803a_reg_dump(struct device *dev, struct f81803a_reg_tab *tab)<br>+{<br>+ uint8_t val;<br>+ for (; tab->reg_name; tab++)<br>+ {<br>+ val = pnp_read_config(dev, tab->reg);<br>+ printk(BIOS_INFO, " %02X %s %02X\n", tab->reg, tab->reg_name, val & 0xff);<br>+ }<br>+<br>+}<br>+static void f81803a_pme_reg_dump(struct device *dev, const char *s)<br>+{<br>+ uint8_t save_clock_select;<br>+ printk(BIOS_INFO, "\nF81803A PME: Regs %s\n", s);<br>+ pnp_enter_conf_mode(dev);<br>+ pnp_write_config(dev, LDN_REG, F81803A_PME);<br>+ /*<br>+ * this is done with two tables as FUNC_PROG_SEL in CLOCK_SELECT_REG<br>+ * is used as a bank select register for the TSI registers index 28<br>+ * We assume that FUNC_PROG_SELECT is 0 for now<br>+ *<br>+ * Note the actual writeup for FUNC_PROG_SEL on page 52 say:<br>+ * "Index 0x29, 0x2B and 0x2C bank select register"<br>+ * However this is not the case and only reg 28 appears to be affected<br>+ * TODO: Confirm this<br>+ */<br>+<br>+ /* read CLOCK_SELECT_REGISTER and save it */<br>+ save_clock_select = pnp_read_config(dev, CLOCK_SELECT_REG);<br>+ /* set FUNC_PROG_SELECT so we read TSI_PIN_SELECT*/<br>+ pnp_write_config(dev, CLOCK_SELECT_REG, save_clock_select | FUNC_PROG_SELECT);<br>+ f81803a_reg_dump(dev, f81803a_pme_regs1);<br>+<br>+ /* now set it back to 0 and read the rest*/<br>+<br>+ pnp_write_config(dev, CLOCK_SELECT_REG, save_clock_select);<br>+ f81803a_reg_dump(dev, f81803a_pme_regs2);<br>+<br>+ pnp_exit_conf_mode(dev);<br>+ printk(BIOS_INFO, "\nF81803A PME: Regs Done %s\n", s);<br>+}<br>+#endif<br> static void f81803a_init(struct device *dev)<br> {<br>+<br>+ printk(BIOS_INFO, "F81803A_INIT.\n");<br> <br> if (!dev->enabled)<br> return;<br>@@ -34,7 +113,19 @@<br> case F81803A_KBC:<br> pc_keyboard_init(NO_AUX_DEVICE);<br> break;<br>+ case F81803A_PME:<br>+#ifdef F81803A_REGDUMP<br>+ f81803a_pme_reg_dump(dev,"before");<br>+#endif<br>+ f81803a_pme_init(dev);<br>+#ifdef F81803A_REGDUMP<br>+ f81803a_pme_reg_dump(dev, "after");<br>+#endif<br>+ break;<br>+<br>+<br> }<br>+<br> }<br> <br> static struct device_operations ops = {<br>@@ -53,12 +144,13 @@<br> { &ops, F81803A_HWM, PNP_IO0 | PNP_IRQ0, 0xff8, },<br> { &ops, F81803A_KBC, PNP_IO0 | PNP_IRQ0 | PNP_IRQ1, 0x07ff, },<br> { &ops, F81803A_GPIO, PNP_IO0 | PNP_IRQ0, 0x7f8, },<br>- { &ops, F81803A_WDT, PNP_IO0, 0x7f8 },<br>+ //{ &ops, F81803A_WDT, PNP_IO0, 0x7f8 },<br> { &ops, F81803A_PME, },<br> };<br> <br> static void enable_dev(struct device *dev)<br> {<br>+ printk(BIOS_INFO, "F81803A : enable_dev\n");<br> pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info);<br> }<br> <br></pre><p>To view, visit <a href="https://review.coreboot.org/21045">change 21045</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/21045"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I025be4d6bcc9de668681b59eb54dbcdbdd092bce </div>
<div style="display:none"> Gerrit-Change-Number: 21045 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: John E. Kabat <sljkrr@gmail.com> </div>
<div style="display:none"> Gerrit-Reviewer: John E. Kabat Jr. <john.kabat@scarletltd.com> </div>