[coreboot-gerrit] Change in coreboot[master]: soc/intel/skylake: Move DMI lock down config after PCI enumeration

[Subrata Banik (Code Review)]

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/21030


Change subject: soc/intel/skylake: Move DMI lock down config after PCI enumeration
......................................................................

soc/intel/skylake: Move DMI lock down config after PCI enumeration

This patch to ensures that coreboot is meeting Intel Silicon
recommendation to performing register lockdown.

TEST=Ensure DMI register offset 0x274c bit 0 is set.

Change-Id: Ie66701d5bd8c8f389e23fb30c8595dd83cf6b1ae
Signed-off-by: Subrata Banik <subrata.banik at intel.com>
---
M src/soc/intel/skylake/finalize.c
M src/soc/intel/skylake/lockdown.c
2 files changed, 15 insertions(+), 7 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/21030/1

diff --git a/src/soc/intel/skylake/finalize.c b/src/soc/intel/skylake/finalize.c
index 3bb1324..53c1c58 100644
--- a/src/soc/intel/skylake/finalize.c
+++ b/src/soc/intel/skylake/finalize.c
@@ -35,8 +35,6 @@
 #include <soc/systemagent.h>
 #include <stdlib.h>
 
-#define PCR_DMI_GCS		0x274C
-#define PCR_DMI_GCS_BILD  	(1 << 0)
 #define PSF_BASE_ADDRESS	0xA00
 #define PCR_PSFX_T0_SHDW_PCIEN	0x1C
 #define PCR_PSFX_T0_SHDW_PCIEN_FUNDIS	(1 << 8)
@@ -154,12 +152,8 @@
 	}
 
 	/* Bios Interface Lock */
-	if (config->LockDownConfigBiosInterface == 0) {
+	if (config->LockDownConfigBiosInterface == 0)
 		fast_spi_set_bios_interface_lock_down();
-
-		/* GCS reg of DMI */
-		pcr_or8(PID_DMI, PCR_DMI_GCS, PCR_DMI_GCS_BILD);
-	}
 
 	/* Bios Lock */
 	if (config->LockDownConfigBiosLock == 0)
diff --git a/src/soc/intel/skylake/lockdown.c b/src/soc/intel/skylake/lockdown.c
index 7564131..e31cf09 100644
--- a/src/soc/intel/skylake/lockdown.c
+++ b/src/soc/intel/skylake/lockdown.c
@@ -17,10 +17,15 @@
 #include <bootstate.h>
 #include <chip.h>
 #include <console/console.h>
+#include <intelblocks/pcr.h>
 #include <soc/lpc.h>
 #include <soc/pci_devs.h>
+#include <soc/pcr_ids.h>
 #include <soc/pm.h>
 #include <string.h>
+
+#define PCR_DMI_GCS		0x274C
+#define PCR_DMI_GCS_BILD  	(1 << 0)
 
 static void lpc_lockdown_config(void)
 {
@@ -68,6 +73,12 @@
 	write32(pmcbase + PMSYNC_TPR_CFG, pmsyncreg);
 }
 
+static void dmi_lockdown_config(void)
+{
+	/* GCS reg of DMI */
+	pcr_or8(PID_DMI, PCR_DMI_GCS, PCR_DMI_GCS_BILD);
+}
+
 static void platform_lockdown_config(void *unused)
 {
 	/* LPC lock down configuration */
@@ -75,6 +86,9 @@
 
 	/* PMC lock down configuration */
 	pmc_lockdown_config();
+
+	/* DMI lock down configuration */
+	dmi_lockdown_config();
 }
 
 BOOT_STATE_INIT_ENTRY(BS_DEV_RESOURCES, BS_ON_EXIT, platform_lockdown_config,

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Ie66701d5bd8c8f389e23fb30c8595dd83cf6b1ae
Gerrit-Change-Number: 21030
Gerrit-PatchSet: 1
Gerrit-Owner: Subrata Banik <subrata.banik at intel.com>
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