<p>Subrata Banik has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/21030">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/intel/skylake: Move DMI lock down config after PCI enumeration<br><br>This patch to ensures that coreboot is meeting Intel Silicon<br>recommendation to performing register lockdown.<br><br>TEST=Ensure DMI register offset 0x274c bit 0 is set.<br><br>Change-Id: Ie66701d5bd8c8f389e23fb30c8595dd83cf6b1ae<br>Signed-off-by: Subrata Banik <subrata.banik@intel.com><br>---<br>M src/soc/intel/skylake/finalize.c<br>M src/soc/intel/skylake/lockdown.c<br>2 files changed, 15 insertions(+), 7 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/21030/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/soc/intel/skylake/finalize.c b/src/soc/intel/skylake/finalize.c<br>index 3bb1324..53c1c58 100644<br>--- a/src/soc/intel/skylake/finalize.c<br>+++ b/src/soc/intel/skylake/finalize.c<br>@@ -35,8 +35,6 @@<br> #include <soc/systemagent.h><br> #include <stdlib.h><br> <br>-#define PCR_DMI_GCS              0x274C<br>-#define PCR_DMI_GCS_BILD       (1 << 0)<br> #define PSF_BASE_ADDRESS       0xA00<br> #define PCR_PSFX_T0_SHDW_PCIEN  0x1C<br> #define PCR_PSFX_T0_SHDW_PCIEN_FUNDIS    (1 << 8)<br>@@ -154,12 +152,8 @@<br>  }<br> <br>  /* Bios Interface Lock */<br>-    if (config->LockDownConfigBiosInterface == 0) {<br>+   if (config->LockDownConfigBiosInterface == 0)<br>              fast_spi_set_bios_interface_lock_down();<br>-<br>-          /* GCS reg of DMI */<br>-         pcr_or8(PID_DMI, PCR_DMI_GCS, PCR_DMI_GCS_BILD);<br>-     }<br> <br>  /* Bios Lock */<br>       if (config->LockDownConfigBiosLock == 0)<br>diff --git a/src/soc/intel/skylake/lockdown.c b/src/soc/intel/skylake/lockdown.c<br>index 7564131..e31cf09 100644<br>--- a/src/soc/intel/skylake/lockdown.c<br>+++ b/src/soc/intel/skylake/lockdown.c<br>@@ -17,10 +17,15 @@<br> #include <bootstate.h><br> #include <chip.h><br> #include <console/console.h><br>+#include <intelblocks/pcr.h><br> #include <soc/lpc.h><br> #include <soc/pci_devs.h><br>+#include <soc/pcr_ids.h><br> #include <soc/pm.h><br> #include <string.h><br>+<br>+#define PCR_DMI_GCS           0x274C<br>+#define PCR_DMI_GCS_BILD       (1 << 0)<br> <br> static void lpc_lockdown_config(void)<br> {<br>@@ -68,6 +73,12 @@<br>     write32(pmcbase + PMSYNC_TPR_CFG, pmsyncreg);<br> }<br> <br>+static void dmi_lockdown_config(void)<br>+{<br>+     /* GCS reg of DMI */<br>+ pcr_or8(PID_DMI, PCR_DMI_GCS, PCR_DMI_GCS_BILD);<br>+}<br>+<br> static void platform_lockdown_config(void *unused)<br> {<br>      /* LPC lock down configuration */<br>@@ -75,6 +86,9 @@<br> <br>       /* PMC lock down configuration */<br>     pmc_lockdown_config();<br>+<br>+    /* DMI lock down configuration */<br>+    dmi_lockdown_config();<br> }<br> <br> BOOT_STATE_INIT_ENTRY(BS_DEV_RESOURCES, BS_ON_EXIT, platform_lockdown_config,<br></pre><p>To view, visit <a href="https://review.coreboot.org/21030">change 21030</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/21030"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Ie66701d5bd8c8f389e23fb30c8595dd83cf6b1ae </div>
<div style="display:none"> Gerrit-Change-Number: 21030 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Subrata Banik <subrata.banik@intel.com> </div>