[coreboot-gerrit] Change in coreboot[master]: soc/intel/skylake: Move PMC lock down config after PCI enumeration

[Subrata Banik (Code Review)]

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/21029


Change subject: soc/intel/skylake: Move PMC lock down config after PCI enumeration
......................................................................

soc/intel/skylake: Move PMC lock down config after PCI enumeration

This patch to ensure that coreboot is meeting Intel Silicon
recommendation to performing register lockdown.

TEST=Ensure PMC MMIO register 0xC4 bit 31 is set.

Change-Id: Ibd86a38fa78752ce007da63a9ccdd991ca21ab92
Signed-off-by: Subrata Banik <subrata.banik at intel.com>
---
M src/soc/intel/skylake/finalize.c
M src/soc/intel/skylake/lockdown.c
2 files changed, 21 insertions(+), 14 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/21029/1

diff --git a/src/soc/intel/skylake/finalize.c b/src/soc/intel/skylake/finalize.c
index 01aa4dd..3bb1324 100644
--- a/src/soc/intel/skylake/finalize.c
+++ b/src/soc/intel/skylake/finalize.c
@@ -92,7 +92,6 @@
 	u16 tcocnt;
 	uint8_t *pmcbase;
 	config_t *config;
-	u32 pmsyncreg;
 	u8 reg8;
 
 	/* Set FAST_SPI opcode menu */
@@ -107,22 +106,11 @@
 	tcocnt |= TCO_LOCK;
 	outw(tcocnt, tcobase + TCO1_CNT);
 
-	/* Lock down ABASE and sleep stretching policy */
-	dev = PCH_DEV_PMC;
-	reg32 = pci_read_config32(dev, GEN_PMCON_B);
-	reg32 |= (SLP_STR_POL_LOCK | ACPI_BASE_LOCK);
-	pci_write_config32(dev, GEN_PMCON_B, reg32);
-
-	/* PMSYNC */
-	pmcbase = pmc_mmio_regs();
-	pmsyncreg = read32(pmcbase + PMSYNC_TPR_CFG);
-	pmsyncreg |= PMSYNC_LOCK;
-	write32(pmcbase + PMSYNC_TPR_CFG, pmsyncreg);
-
 	/* Display me status before we hide it */
 	intel_me_status();
 
-	/* we should disable Heci1 based on the devicetree policy */
+	dev = PCH_DEV_PMC;
+	pmcbase = pmc_mmio_regs();
 	config = dev->chip_info;
 
 	/*
diff --git a/src/soc/intel/skylake/lockdown.c b/src/soc/intel/skylake/lockdown.c
index a61e423..7564131 100644
--- a/src/soc/intel/skylake/lockdown.c
+++ b/src/soc/intel/skylake/lockdown.c
@@ -19,6 +19,7 @@
 #include <console/console.h>
 #include <soc/lpc.h>
 #include <soc/pci_devs.h>
+#include <soc/pm.h>
 #include <string.h>
 
 static void lpc_lockdown_config(void)
@@ -52,10 +53,28 @@
 	pci_read_config8(dev, BIOS_CNTL);
 }
 
+static void pmc_lockdown_config(void)
+{
+	struct device *dev;
+	uint8_t *pmcbase;
+	u32 pmsyncreg;
+
+	dev = PCH_DEV_PMC;
+
+	/* PMSYNC */
+	pmcbase = pmc_mmio_regs();
+	pmsyncreg = read32(pmcbase + PMSYNC_TPR_CFG);
+	pmsyncreg |= PMSYNC_LOCK;
+	write32(pmcbase + PMSYNC_TPR_CFG, pmsyncreg);
+}
+
 static void platform_lockdown_config(void *unused)
 {
 	/* LPC lock down configuration */
 	lpc_lockdown_config();
+
+	/* PMC lock down configuration */
+	pmc_lockdown_config();
 }
 
 BOOT_STATE_INIT_ENTRY(BS_DEV_RESOURCES, BS_ON_EXIT, platform_lockdown_config,

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Ibd86a38fa78752ce007da63a9ccdd991ca21ab92
Gerrit-Change-Number: 21029
Gerrit-PatchSet: 1
Gerrit-Owner: Subrata Banik <subrata.banik at intel.com>
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