<p>Subrata Banik has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/21029">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/intel/skylake: Move PMC lock down config after PCI enumeration<br><br>This patch to ensure that coreboot is meeting Intel Silicon<br>recommendation to performing register lockdown.<br><br>TEST=Ensure PMC MMIO register 0xC4 bit 31 is set.<br><br>Change-Id: Ibd86a38fa78752ce007da63a9ccdd991ca21ab92<br>Signed-off-by: Subrata Banik <subrata.banik@intel.com><br>---<br>M src/soc/intel/skylake/finalize.c<br>M src/soc/intel/skylake/lockdown.c<br>2 files changed, 21 insertions(+), 14 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/21029/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/soc/intel/skylake/finalize.c b/src/soc/intel/skylake/finalize.c<br>index 01aa4dd..3bb1324 100644<br>--- a/src/soc/intel/skylake/finalize.c<br>+++ b/src/soc/intel/skylake/finalize.c<br>@@ -92,7 +92,6 @@<br>         u16 tcocnt;<br>   uint8_t *pmcbase;<br>     config_t *config;<br>-    u32 pmsyncreg;<br>        u8 reg8;<br> <br>   /* Set FAST_SPI opcode menu */<br>@@ -107,22 +106,11 @@<br>         tcocnt |= TCO_LOCK;<br>   outw(tcocnt, tcobase + TCO1_CNT);<br> <br>- /* Lock down ABASE and sleep stretching policy */<br>-    dev = PCH_DEV_PMC;<br>-   reg32 = pci_read_config32(dev, GEN_PMCON_B);<br>- reg32 |= (SLP_STR_POL_LOCK | ACPI_BASE_LOCK);<br>-        pci_write_config32(dev, GEN_PMCON_B, reg32);<br>-<br>-      /* PMSYNC */<br>- pmcbase = pmc_mmio_regs();<br>-   pmsyncreg = read32(pmcbase + PMSYNC_TPR_CFG);<br>-        pmsyncreg |= PMSYNC_LOCK;<br>-    write32(pmcbase + PMSYNC_TPR_CFG, pmsyncreg);<br>-<br>      /* Display me status before we hide it */<br>     intel_me_status();<br> <br>-        /* we should disable Heci1 based on the devicetree policy */<br>+ dev = PCH_DEV_PMC;<br>+   pmcbase = pmc_mmio_regs();<br>    config = dev->chip_info;<br> <br>        /*<br>diff --git a/src/soc/intel/skylake/lockdown.c b/src/soc/intel/skylake/lockdown.c<br>index a61e423..7564131 100644<br>--- a/src/soc/intel/skylake/lockdown.c<br>+++ b/src/soc/intel/skylake/lockdown.c<br>@@ -19,6 +19,7 @@<br> #include <console/console.h><br> #include <soc/lpc.h><br> #include <soc/pci_devs.h><br>+#include <soc/pm.h><br> #include <string.h><br> <br> static void lpc_lockdown_config(void)<br>@@ -52,10 +53,28 @@<br>    pci_read_config8(dev, BIOS_CNTL);<br> }<br> <br>+static void pmc_lockdown_config(void)<br>+{<br>+ struct device *dev;<br>+  uint8_t *pmcbase;<br>+    u32 pmsyncreg;<br>+<br>+    dev = PCH_DEV_PMC;<br>+<br>+        /* PMSYNC */<br>+ pmcbase = pmc_mmio_regs();<br>+   pmsyncreg = read32(pmcbase + PMSYNC_TPR_CFG);<br>+        pmsyncreg |= PMSYNC_LOCK;<br>+    write32(pmcbase + PMSYNC_TPR_CFG, pmsyncreg);<br>+}<br>+<br> static void platform_lockdown_config(void *unused)<br> {<br>         /* LPC lock down configuration */<br>     lpc_lockdown_config();<br>+<br>+    /* PMC lock down configuration */<br>+    pmc_lockdown_config();<br> }<br> <br> BOOT_STATE_INIT_ENTRY(BS_DEV_RESOURCES, BS_ON_EXIT, platform_lockdown_config,<br></pre><p>To view, visit <a href="https://review.coreboot.org/21029">change 21029</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/21029"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Ibd86a38fa78752ce007da63a9ccdd991ca21ab92 </div>
<div style="display:none"> Gerrit-Change-Number: 21029 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Subrata Banik <subrata.banik@intel.com> </div>