[coreboot-gerrit] Change in coreboot[master]: intel/common/block/fast_spi: Add config option to disable write status

[Duncan Laurie (Code Review)]

Duncan Laurie has uploaded this change for review. ( https://review.coreboot.org/21021


Change subject: intel/common/block/fast_spi: Add config option to disable write status
......................................................................

intel/common/block/fast_spi: Add config option to disable write status

Chrome OS systems rely on the write status register to enable/disable
flash write protection and disabling this opcode breaks the ability
to enable or disable write protection with flashrom.

Add a configure option for this feature that will disable the opcode
for Write Status commands unless CONFIG_CHROMEOS is enabled.

Tested to ensure that a default build without CONFIG_CHROMEOS has this
option enabled while a build with CONFIG_CHROMEOS does not.  Also
ensured that when this option is disabled (for Chrome OS) then flashrom
can be used with the --wp-enable and --wp-disable commands, depending
on the state of the external write protect pin.

Change-Id: Ia2ef3c3b1e10fba2c437e083f3537022f1fce84a
Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
---
M src/soc/intel/common/block/fast_spi/Kconfig
M src/soc/intel/common/block/fast_spi/fast_spi.c
2 files changed, 12 insertions(+), 1 deletion(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/21021/1

diff --git a/src/soc/intel/common/block/fast_spi/Kconfig b/src/soc/intel/common/block/fast_spi/Kconfig
index 87edb92..4bd1f59 100644
--- a/src/soc/intel/common/block/fast_spi/Kconfig
+++ b/src/soc/intel/common/block/fast_spi/Kconfig
@@ -2,3 +2,11 @@
 	bool
 	help
 	  Intel Processor common FAST_SPI support
+
+config FAST_SPI_DISABLE_WRITE_STATUS
+	bool "Disable write status SPI opcode"
+	depends on SOC_INTEL_COMMON_BLOCK_FAST_SPI
+	default n if CHROMEOS
+	default y
+	help
+	  Disable the write status SPI opcode in Intel Fast SPI block.
diff --git a/src/soc/intel/common/block/fast_spi/fast_spi.c b/src/soc/intel/common/block/fast_spi/fast_spi.c
index fe0217a..f7ef685 100644
--- a/src/soc/intel/common/block/fast_spi/fast_spi.c
+++ b/src/soc/intel/common/block/fast_spi/fast_spi.c
@@ -144,7 +144,10 @@
 void fast_spi_lock_bar(void)
 {
 	void *spibar = fast_spi_get_bar();
-	const uint16_t hsfs = SPIBAR_HSFSTS_FLOCKDN | SPIBAR_HSFSTS_WRSDIS;
+	uint16_t hsfs = SPIBAR_HSFSTS_FLOCKDN;
+
+	if (IS_ENABLED(CONFIG_FAST_SPI_DISABLE_WRITE_STATUS))
+		hsfs |= SPIBAR_HSFSTS_WRSDIS;
 
 	write16(spibar + SPIBAR_HSFSTS_CTL, hsfs);
 }

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Ia2ef3c3b1e10fba2c437e083f3537022f1fce84a
Gerrit-Change-Number: 21021
Gerrit-PatchSet: 1
Gerrit-Owner: Duncan Laurie <dlaurie at chromium.org>
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