<p>Duncan Laurie has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/21021">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">intel/common/block/fast_spi: Add config option to disable write status<br><br>Chrome OS systems rely on the write status register to enable/disable<br>flash write protection and disabling this opcode breaks the ability<br>to enable or disable write protection with flashrom.<br><br>Add a configure option for this feature that will disable the opcode<br>for Write Status commands unless CONFIG_CHROMEOS is enabled.<br><br>Tested to ensure that a default build without CONFIG_CHROMEOS has this<br>option enabled while a build with CONFIG_CHROMEOS does not.  Also<br>ensured that when this option is disabled (for Chrome OS) then flashrom<br>can be used with the --wp-enable and --wp-disable commands, depending<br>on the state of the external write protect pin.<br><br>Change-Id: Ia2ef3c3b1e10fba2c437e083f3537022f1fce84a<br>Signed-off-by: Duncan Laurie <dlaurie@chromium.org><br>---<br>M src/soc/intel/common/block/fast_spi/Kconfig<br>M src/soc/intel/common/block/fast_spi/fast_spi.c<br>2 files changed, 12 insertions(+), 1 deletion(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/21021/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/soc/intel/common/block/fast_spi/Kconfig b/src/soc/intel/common/block/fast_spi/Kconfig<br>index 87edb92..4bd1f59 100644<br>--- a/src/soc/intel/common/block/fast_spi/Kconfig<br>+++ b/src/soc/intel/common/block/fast_spi/Kconfig<br>@@ -2,3 +2,11 @@<br>   bool<br>  help<br>    Intel Processor common FAST_SPI support<br>+<br>+config FAST_SPI_DISABLE_WRITE_STATUS<br>+  bool "Disable write status SPI opcode"<br>+     depends on SOC_INTEL_COMMON_BLOCK_FAST_SPI<br>+   default n if CHROMEOS<br>+        default y<br>+    help<br>+   Disable the write status SPI opcode in Intel Fast SPI block.<br>diff --git a/src/soc/intel/common/block/fast_spi/fast_spi.c b/src/soc/intel/common/block/fast_spi/fast_spi.c<br>index fe0217a..f7ef685 100644<br>--- a/src/soc/intel/common/block/fast_spi/fast_spi.c<br>+++ b/src/soc/intel/common/block/fast_spi/fast_spi.c<br>@@ -144,7 +144,10 @@<br> void fast_spi_lock_bar(void)<br> {<br>      void *spibar = fast_spi_get_bar();<br>-   const uint16_t hsfs = SPIBAR_HSFSTS_FLOCKDN | SPIBAR_HSFSTS_WRSDIS;<br>+  uint16_t hsfs = SPIBAR_HSFSTS_FLOCKDN;<br>+<br>+    if (IS_ENABLED(CONFIG_FAST_SPI_DISABLE_WRITE_STATUS))<br>+                hsfs |= SPIBAR_HSFSTS_WRSDIS;<br> <br>      write16(spibar + SPIBAR_HSFSTS_CTL, hsfs);<br> }<br></pre><p>To view, visit <a href="https://review.coreboot.org/21021">change 21021</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/21021"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Ia2ef3c3b1e10fba2c437e083f3537022f1fce84a </div>
<div style="display:none"> Gerrit-Change-Number: 21021 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Duncan Laurie <dlaurie@chromium.org> </div>