[coreboot-gerrit] Change in coreboot[master]: soc/intel/apollolake: Rename SRAM BAR0 and BAR2 macros

[V Sowmya (Code Review)]

V Sowmya has uploaded this change for review. ( https://review.coreboot.org/20539


Change subject: soc/intel/apollolake: Rename SRAM BAR0 and BAR2 macros
......................................................................

soc/intel/apollolake: Rename SRAM BAR0 and BAR2 macros

Rename BAR0 and BAR2 SRAM base and size macros to align with the spec.
* PMC_SRAM_BASE_0 -> SRAM_BASE_0
* PMC_SRAM_SIZE_0 -> SRAM_BASE_0
* PMC_SRAM_BASE_1 -> SRAM_BASE_2
* PMC_SRAM_SIZE_1 -> SRAM_BASE_2

Change-Id: I48d65c30368c4500549b535341b14ca262d7fc48
Signed-off-by: V Sowmya <v.sowmya at intel.com>
---
M src/soc/intel/apollolake/acpi/pmc_ipc.asl
M src/soc/intel/apollolake/include/soc/iomap.h
M src/soc/intel/apollolake/sram.c
3 files changed, 11 insertions(+), 11 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/20539/2

diff --git a/src/soc/intel/apollolake/acpi/pmc_ipc.asl b/src/soc/intel/apollolake/acpi/pmc_ipc.asl
index 8aeaef6..5c53af4 100644
--- a/src/soc/intel/apollolake/acpi/pmc_ipc.asl
+++ b/src/soc/intel/apollolake/acpi/pmc_ipc.asl
@@ -52,9 +52,9 @@
 			Store (MCH_BASE_ADDRESS + MAILBOX_INTF, MIBA)
 
 			CreateDwordField (^RBUF, ^SBAR._BAS, SBAS)
-			Store (PMC_SRAM_BASE_0, SBAS)
+			Store (SRAM_BASE_0, SBAS)
 
 			Return (^RBUF)
 		}
 	}
-}
\ No newline at end of file
+}
diff --git a/src/soc/intel/apollolake/include/soc/iomap.h b/src/soc/intel/apollolake/include/soc/iomap.h
index a8e4bc9..c3eb66b 100644
--- a/src/soc/intel/apollolake/include/soc/iomap.h
+++ b/src/soc/intel/apollolake/include/soc/iomap.h
@@ -39,10 +39,10 @@
 #define PMC_BAR1			0xfe044000
 #define PMC_BAR0_SIZE			(8 * KiB)
 
-#define PMC_SRAM_BASE_0			0xfe900000
-#define PMC_SRAM_SIZE_0			(8 * KiB)
-#define PMC_SRAM_BASE_1			0xfe902000
-#define PMC_SRAM_SIZE_1			(4 * KiB)
+#define SRAM_BASE_0			0xfe900000
+#define SRAM_SIZE_0			(8 * KiB)
+#define SRAM_BASE_2			0xfe902000
+#define SRAM_SIZE_2			(4 * KiB)
 
 /* Temporary BAR for SPI until PCI enumeration assigns a BAR in ramstage. */
 #define PRERAM_SPI_BASE_ADDRESS		0xfe010000
diff --git a/src/soc/intel/apollolake/sram.c b/src/soc/intel/apollolake/sram.c
index 0225327..70e1330 100644
--- a/src/soc/intel/apollolake/sram.c
+++ b/src/soc/intel/apollolake/sram.c
@@ -26,13 +26,13 @@
 	pci_dev_read_resources(dev);
 
 	res = new_resource(dev, PCI_BASE_ADDRESS_0);
-	res->base = PMC_SRAM_BASE_0;
-	res->size = PMC_SRAM_SIZE_0;
+	res->base = SRAM_BASE_0;
+	res->size = SRAM_SIZE_0;
 	res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
 
 	res = new_resource(dev, PCI_BASE_ADDRESS_2);
-	res->base = PMC_SRAM_BASE_1;
-	res->size = PMC_SRAM_SIZE_1;
+	res->base = SRAM_BASE_2;
+	res->size = SRAM_SIZE_2;
 	res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
 }
 
@@ -51,7 +51,7 @@
 	pci_write_config32(dev, res->index, res->base);
 	dev->command |= PCI_COMMAND_MEMORY;
 	res->flags |= IORESOURCE_STORED;
-	report_resource_stored(dev, res, " SRAM BAR 1");
+	report_resource_stored(dev, res, " SRAM BAR 2");
 }
 
 static const struct device_operations device_ops = {

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I48d65c30368c4500549b535341b14ca262d7fc48
Gerrit-Change-Number: 20539
Gerrit-PatchSet: 2
Gerrit-Owner: V Sowmya <v.sowmya at intel.com>
Gerrit-Reviewer: Aaron Durbin <adurbin at chromium.org>
Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan at intel.com>
Gerrit-Reviewer: Bora Guvendik <bora.guvendik at intel.com>
Gerrit-Reviewer: Hannah Williams <hannah.williams at intel.com>
Gerrit-Reviewer: Lijian Zhao <lijian.zhao at intel.com>
Gerrit-Reviewer: Subrata Banik <subrata.banik at intel.com>
Gerrit-Reviewer: V Sowmya <v.sowmya at intel.com>
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