<p>V Sowmya has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/20539">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/intel/apollolake: Rename SRAM BAR0 and BAR2 macros<br><br>Rename BAR0 and BAR2 SRAM base and size macros to align with the spec.<br>* PMC_SRAM_BASE_0 -> SRAM_BASE_0<br>* PMC_SRAM_SIZE_0 -> SRAM_BASE_0<br>* PMC_SRAM_BASE_1 -> SRAM_BASE_2<br>* PMC_SRAM_SIZE_1 -> SRAM_BASE_2<br><br>Change-Id: I48d65c30368c4500549b535341b14ca262d7fc48<br>Signed-off-by: V Sowmya <v.sowmya@intel.com><br>---<br>M src/soc/intel/apollolake/acpi/pmc_ipc.asl<br>M src/soc/intel/apollolake/include/soc/iomap.h<br>M src/soc/intel/apollolake/sram.c<br>3 files changed, 11 insertions(+), 11 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/20539/2</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/soc/intel/apollolake/acpi/pmc_ipc.asl b/src/soc/intel/apollolake/acpi/pmc_ipc.asl<br>index 8aeaef6..5c53af4 100644<br>--- a/src/soc/intel/apollolake/acpi/pmc_ipc.asl<br>+++ b/src/soc/intel/apollolake/acpi/pmc_ipc.asl<br>@@ -52,9 +52,9 @@<br>                       Store (MCH_BASE_ADDRESS + MAILBOX_INTF, MIBA)<br> <br>                      CreateDwordField (^RBUF, ^SBAR._BAS, SBAS)<br>-                   Store (PMC_SRAM_BASE_0, SBAS)<br>+                        Store (SRAM_BASE_0, SBAS)<br> <br>                  Return (^RBUF)<br>                }<br>     }<br>-}<br>\ No newline at end of file<br>+}<br>diff --git a/src/soc/intel/apollolake/include/soc/iomap.h b/src/soc/intel/apollolake/include/soc/iomap.h<br>index a8e4bc9..c3eb66b 100644<br>--- a/src/soc/intel/apollolake/include/soc/iomap.h<br>+++ b/src/soc/intel/apollolake/include/soc/iomap.h<br>@@ -39,10 +39,10 @@<br> #define PMC_BAR1                 0xfe044000<br> #define PMC_BAR0_SIZE                      (8 * KiB)<br> <br>-#define PMC_SRAM_BASE_0                  0xfe900000<br>-#define PMC_SRAM_SIZE_0                    (8 * KiB)<br>-#define PMC_SRAM_BASE_1                     0xfe902000<br>-#define PMC_SRAM_SIZE_1                    (4 * KiB)<br>+#define SRAM_BASE_0                 0xfe900000<br>+#define SRAM_SIZE_0                        (8 * KiB)<br>+#define SRAM_BASE_2                 0xfe902000<br>+#define SRAM_SIZE_2                        (4 * KiB)<br> <br> /* Temporary BAR for SPI until PCI enumeration assigns a BAR in ramstage. */<br> #define PRERAM_SPI_BASE_ADDRESS           0xfe010000<br>diff --git a/src/soc/intel/apollolake/sram.c b/src/soc/intel/apollolake/sram.c<br>index 0225327..70e1330 100644<br>--- a/src/soc/intel/apollolake/sram.c<br>+++ b/src/soc/intel/apollolake/sram.c<br>@@ -26,13 +26,13 @@<br>  pci_dev_read_resources(dev);<br> <br>       res = new_resource(dev, PCI_BASE_ADDRESS_0);<br>- res->base = PMC_SRAM_BASE_0;<br>-      res->size = PMC_SRAM_SIZE_0;<br>+      res->base = SRAM_BASE_0;<br>+  res->size = SRAM_SIZE_0;<br>   res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;<br> <br>   res = new_resource(dev, PCI_BASE_ADDRESS_2);<br>- res->base = PMC_SRAM_BASE_1;<br>-      res->size = PMC_SRAM_SIZE_1;<br>+      res->base = SRAM_BASE_2;<br>+  res->size = SRAM_SIZE_2;<br>   res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;<br> }<br> <br>@@ -51,7 +51,7 @@<br>    pci_write_config32(dev, res->index, res->base);<br>         dev->command |= PCI_COMMAND_MEMORY;<br>        res->flags |= IORESOURCE_STORED;<br>-  report_resource_stored(dev, res, " SRAM BAR 1");<br>+   report_resource_stored(dev, res, " SRAM BAR 2");<br> }<br> <br> static const struct device_operations device_ops = {<br></pre><p>To view, visit <a href="https://review.coreboot.org/20539">change 20539</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/20539"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I48d65c30368c4500549b535341b14ca262d7fc48 </div>
<div style="display:none"> Gerrit-Change-Number: 20539 </div>
<div style="display:none"> Gerrit-PatchSet: 2 </div>
<div style="display:none"> Gerrit-Owner: V Sowmya <v.sowmya@intel.com> </div>
<div style="display:none"> Gerrit-Reviewer: Aaron Durbin <adurbin@chromium.org> </div>
<div style="display:none"> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan@intel.com> </div>
<div style="display:none"> Gerrit-Reviewer: Bora Guvendik <bora.guvendik@intel.com> </div>
<div style="display:none"> Gerrit-Reviewer: Hannah Williams <hannah.williams@intel.com> </div>
<div style="display:none"> Gerrit-Reviewer: Lijian Zhao <lijian.zhao@intel.com> </div>
<div style="display:none"> Gerrit-Reviewer: Subrata Banik <subrata.banik@intel.com> </div>
<div style="display:none"> Gerrit-Reviewer: V Sowmya <v.sowmya@intel.com> </div>