[coreboot-gerrit] Change in coreboot[master]: nb/amd/mct: Don't include all needed headers in mct_d.h
Arthur Heymans (Code Review)
gerrit at coreboot.org
Sat Aug 12 21:04:42 CEST 2017
Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/20972
Change subject: nb/amd/mct: Don't include all needed headers in mct_d.h
......................................................................
nb/amd/mct: Don't include all needed headers in mct_d.h
Include header that the *.c files need in the *.c file itself.
Change-Id: I454eb9f00c8ffebd7a48bf9cb65d012b3fc335f2
Signed-off-by: Arthur Heymans <arthur at aheymans.xyz>
---
M src/northbridge/amd/amdmct/mct/mct_d.c
M src/northbridge/amd/amdmct/mct/mct_d.h
M src/northbridge/amd/amdmct/mct/mctardk4.c
M src/northbridge/amd/amdmct/mct/mctcsi_d.c
M src/northbridge/amd/amdmct/mct/mctdqs_d.c
M src/northbridge/amd/amdmct/mct/mctmtr_d.c
M src/northbridge/amd/amdmct/mct/mctndi_d.c
M src/northbridge/amd/amdmct/mct/mctpro_d.c
M src/northbridge/amd/amdmct/mct/mctsrc.c
M src/northbridge/amd/amdmct/mct/mcttmrl.c
10 files changed, 28 insertions(+), 11 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/20972/1
diff --git a/src/northbridge/amd/amdmct/mct/mct_d.c b/src/northbridge/amd/amdmct/mct/mct_d.c
index ea619a3..802b5a4 100644
--- a/src/northbridge/amd/amdmct/mct/mct_d.c
+++ b/src/northbridge/amd/amdmct/mct/mct_d.c
@@ -33,11 +33,14 @@
* supported.
*/
+#include <console/console.h>
#include <northbridge/amd/amdfam10/debug.h>
-#include "mct_d.h"
-
#include <string.h>
+#include "mct_d.h"
+#include "mct_d_gcc.h"
+
+
static u8 ReconfigureDIMMspare_D(struct MCTStatStruc *pMCTstat,
struct DCTStatStruc *pDCTstatA);
static void DQSTiming_D(struct MCTStatStruc *pMCTstat,
diff --git a/src/northbridge/amd/amdmct/mct/mct_d.h b/src/northbridge/amd/amdmct/mct/mct_d.h
index 29a7876..5e46173 100644
--- a/src/northbridge/amd/amdmct/mct/mct_d.h
+++ b/src/northbridge/amd/amdmct/mct/mct_d.h
@@ -22,10 +22,6 @@
#define DQS_TRAIN_DEBUG 0
-#include <inttypes.h>
-#include <compiler.h>
-#include "mct_d_gcc.h"
-#include <console/console.h>
#include <northbridge/amd/amdfam10/raminit.h>
extern const u8 Table_DQSRcvEn_Offset[];
@@ -707,7 +703,6 @@
#define NV_MAX_DIMMS_PER_CH 64 /* Maximum number of DIMMs per channel */
-#include <northbridge/amd/amdfam10/amdfam10.h>
/*===============================================================================
CBMEM storage
diff --git a/src/northbridge/amd/amdmct/mct/mctardk4.c b/src/northbridge/amd/amdmct/mct/mctardk4.c
index 29861e7..89dd393 100644
--- a/src/northbridge/amd/amdmct/mct/mctardk4.c
+++ b/src/northbridge/amd/amdmct/mct/mctardk4.c
@@ -15,7 +15,9 @@
#include <inttypes.h>
#include <northbridge/amd/amdfam10/debug.h>
+
#include "mct_d.h"
+#include "mct_d_gcc.h"
static void Get_ChannelPS_Cfg0_D(u8 MAAdimms, u8 Speed, u8 MAAload,
u8 DATAAload, u32 *AddrTmgCTL, u32 *ODC_CTL,
diff --git a/src/northbridge/amd/amdmct/mct/mctcsi_d.c b/src/northbridge/amd/amdmct/mct/mctcsi_d.c
index 08acc03..829892d 100644
--- a/src/northbridge/amd/amdmct/mct/mctcsi_d.c
+++ b/src/northbridge/amd/amdmct/mct/mctcsi_d.c
@@ -14,7 +14,9 @@
*/
#include <northbridge/amd/amdfam10/debug.h>
+
#include "mct_d.h"
+#include "mct_d_gcc.h"
/* Low swap bit vs bank size encoding (physical, not logical address bit)
* ;To calculate the number by hand, add the number of Bank address bits
diff --git a/src/northbridge/amd/amdmct/mct/mctdqs_d.c b/src/northbridge/amd/amdmct/mct/mctdqs_d.c
index 3146bfd..174c481 100644
--- a/src/northbridge/amd/amdmct/mct/mctdqs_d.c
+++ b/src/northbridge/amd/amdmct/mct/mctdqs_d.c
@@ -14,10 +14,12 @@
*/
#include <northbridge/amd/amdfam10/debug.h>
-#include "mct_d.h"
#include <cpu/x86/cr.h>
#include <cpu/amd/mtrr.h>
+#include "mct_d.h"
+#include "mct_d_gcc.h"
+
static void CalcEccDQSPos_D(struct MCTStatStruc *pMCTstat,
struct DCTStatStruc *pDCTstat, u16 like,
u8 scale, u8 ChipSel);
diff --git a/src/northbridge/amd/amdmct/mct/mctmtr_d.c b/src/northbridge/amd/amdmct/mct/mctmtr_d.c
index 0a157ed..ce5a60c 100644
--- a/src/northbridge/amd/amdmct/mct/mctmtr_d.c
+++ b/src/northbridge/amd/amdmct/mct/mctmtr_d.c
@@ -14,9 +14,11 @@
*/
#include <northbridge/amd/amdfam10/debug.h>
-#include "mct_d.h"
#include <cpu/amd/mtrr.h>
+#include "mct_d.h"
+#include "mct_d_gcc.h"
+
static void SetMTRRrangeWB_D(u32 Base, u32 *pLimit, u32 *pMtrrAddr);
static void SetMTRRrange_D(u32 Base, u32 *pLimit, u32 *pMtrrAddr, u16 MtrrType);
diff --git a/src/northbridge/amd/amdmct/mct/mctndi_d.c b/src/northbridge/amd/amdmct/mct/mctndi_d.c
index fe2bf9e..a95f1c9 100644
--- a/src/northbridge/amd/amdmct/mct/mctndi_d.c
+++ b/src/northbridge/amd/amdmct/mct/mctndi_d.c
@@ -15,7 +15,10 @@
*/
#include <northbridge/amd/amdfam10/debug.h>
+
#include "mct_d.h"
+#include "mct_d_gcc.h"
+
void InterleaveNodes_D(struct MCTStatStruc *pMCTstat,
struct DCTStatStruc *pDCTstatA)
diff --git a/src/northbridge/amd/amdmct/mct/mctpro_d.c b/src/northbridge/amd/amdmct/mct/mctpro_d.c
index 18d69b5..90f1a42 100644
--- a/src/northbridge/amd/amdmct/mct/mctpro_d.c
+++ b/src/northbridge/amd/amdmct/mct/mctpro_d.c
@@ -15,7 +15,10 @@
*/
#include <northbridge/amd/amdfam10/debug.h>
+
#include "mct_d.h"
+#include "mct_d_gcc.h"
+
void EarlySampleSupport_D(void)
{
diff --git a/src/northbridge/amd/amdmct/mct/mctsrc.c b/src/northbridge/amd/amdmct/mct/mctsrc.c
index c53b947..3a78620 100644
--- a/src/northbridge/amd/amdmct/mct/mctsrc.c
+++ b/src/northbridge/amd/amdmct/mct/mctsrc.c
@@ -15,9 +15,12 @@
*/
#include <northbridge/amd/amdfam10/debug.h>
-#include "mct_d.h"
#include <cpu/x86/cr.h>
+#include "mct_d.h"
+#include "mct_d_gcc.h"
+
+
/******************************************************************************
Description: Receiver En and DQS Timing Training feature for DDR 2 MCT
******************************************************************************/
diff --git a/src/northbridge/amd/amdmct/mct/mcttmrl.c b/src/northbridge/amd/amdmct/mct/mcttmrl.c
index 4c6d8e6..81ec5f9 100644
--- a/src/northbridge/amd/amdmct/mct/mcttmrl.c
+++ b/src/northbridge/amd/amdmct/mct/mcttmrl.c
@@ -13,9 +13,11 @@
* GNU General Public License for more details.
*/
-#include "mct_d.h"
#include <cpu/x86/cr.h>
+#include "mct_d.h"
+#include "mct_d_gcc.h"
+
/*
* Description: Max Read Latency Training feature for DDR 2 MCT
*/
--
To view, visit https://review.coreboot.org/20972
To unsubscribe, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I454eb9f00c8ffebd7a48bf9cb65d012b3fc335f2
Gerrit-Change-Number: 20972
Gerrit-PatchSet: 1
Gerrit-Owner: Arthur Heymans <arthur at aheymans.xyz>
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://mail.coreboot.org/pipermail/coreboot-gerrit/attachments/20170812/6e666b16/attachment-0001.html>
More information about the coreboot-gerrit
mailing list