<p>Arthur Heymans has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/20972">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">nb/amd/mct: Don't include all needed headers in mct_d.h<br><br>Include header that the *.c files need in the *.c file itself.<br><br>Change-Id: I454eb9f00c8ffebd7a48bf9cb65d012b3fc335f2<br>Signed-off-by: Arthur Heymans <arthur@aheymans.xyz><br>---<br>M src/northbridge/amd/amdmct/mct/mct_d.c<br>M src/northbridge/amd/amdmct/mct/mct_d.h<br>M src/northbridge/amd/amdmct/mct/mctardk4.c<br>M src/northbridge/amd/amdmct/mct/mctcsi_d.c<br>M src/northbridge/amd/amdmct/mct/mctdqs_d.c<br>M src/northbridge/amd/amdmct/mct/mctmtr_d.c<br>M src/northbridge/amd/amdmct/mct/mctndi_d.c<br>M src/northbridge/amd/amdmct/mct/mctpro_d.c<br>M src/northbridge/amd/amdmct/mct/mctsrc.c<br>M src/northbridge/amd/amdmct/mct/mcttmrl.c<br>10 files changed, 28 insertions(+), 11 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/20972/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/northbridge/amd/amdmct/mct/mct_d.c b/src/northbridge/amd/amdmct/mct/mct_d.c<br>index ea619a3..802b5a4 100644<br>--- a/src/northbridge/amd/amdmct/mct/mct_d.c<br>+++ b/src/northbridge/amd/amdmct/mct/mct_d.c<br>@@ -33,11 +33,14 @@<br> * supported.<br> */<br> <br>+#include <console/console.h><br> #include <northbridge/amd/amdfam10/debug.h><br>-#include "mct_d.h"<br>-<br> #include <string.h><br> <br>+#include "mct_d.h"<br>+#include "mct_d_gcc.h"<br>+<br>+<br> static u8 ReconfigureDIMMspare_D(struct MCTStatStruc *pMCTstat,<br> struct DCTStatStruc *pDCTstatA);<br> static void DQSTiming_D(struct MCTStatStruc *pMCTstat,<br>diff --git a/src/northbridge/amd/amdmct/mct/mct_d.h b/src/northbridge/amd/amdmct/mct/mct_d.h<br>index 29a7876..5e46173 100644<br>--- a/src/northbridge/amd/amdmct/mct/mct_d.h<br>+++ b/src/northbridge/amd/amdmct/mct/mct_d.h<br>@@ -22,10 +22,6 @@<br> <br> #define DQS_TRAIN_DEBUG 0<br> <br>-#include <inttypes.h><br>-#include <compiler.h><br>-#include "mct_d_gcc.h"<br>-#include <console/console.h><br> #include <northbridge/amd/amdfam10/raminit.h><br> <br> extern const u8 Table_DQSRcvEn_Offset[];<br>@@ -707,7 +703,6 @@<br> <br> #define NV_MAX_DIMMS_PER_CH 64 /* Maximum number of DIMMs per channel */<br> <br>-#include <northbridge/amd/amdfam10/amdfam10.h><br> <br> /*===============================================================================<br> CBMEM storage<br>diff --git a/src/northbridge/amd/amdmct/mct/mctardk4.c b/src/northbridge/amd/amdmct/mct/mctardk4.c<br>index 29861e7..89dd393 100644<br>--- a/src/northbridge/amd/amdmct/mct/mctardk4.c<br>+++ b/src/northbridge/amd/amdmct/mct/mctardk4.c<br>@@ -15,7 +15,9 @@<br> <br> #include <inttypes.h><br> #include <northbridge/amd/amdfam10/debug.h><br>+<br> #include "mct_d.h"<br>+#include "mct_d_gcc.h"<br> <br> static void Get_ChannelPS_Cfg0_D(u8 MAAdimms, u8 Speed, u8 MAAload,<br> u8 DATAAload, u32 *AddrTmgCTL, u32 *ODC_CTL,<br>diff --git a/src/northbridge/amd/amdmct/mct/mctcsi_d.c b/src/northbridge/amd/amdmct/mct/mctcsi_d.c<br>index 08acc03..829892d 100644<br>--- a/src/northbridge/amd/amdmct/mct/mctcsi_d.c<br>+++ b/src/northbridge/amd/amdmct/mct/mctcsi_d.c<br>@@ -14,7 +14,9 @@<br> */<br> <br> #include <northbridge/amd/amdfam10/debug.h><br>+<br> #include "mct_d.h"<br>+#include "mct_d_gcc.h"<br> <br> /* Low swap bit vs bank size encoding (physical, not logical address bit)<br> * ;To calculate the number by hand, add the number of Bank address bits<br>diff --git a/src/northbridge/amd/amdmct/mct/mctdqs_d.c b/src/northbridge/amd/amdmct/mct/mctdqs_d.c<br>index 3146bfd..174c481 100644<br>--- a/src/northbridge/amd/amdmct/mct/mctdqs_d.c<br>+++ b/src/northbridge/amd/amdmct/mct/mctdqs_d.c<br>@@ -14,10 +14,12 @@<br> */<br> <br> #include <northbridge/amd/amdfam10/debug.h><br>-#include "mct_d.h"<br> #include <cpu/x86/cr.h><br> #include <cpu/amd/mtrr.h><br> <br>+#include "mct_d.h"<br>+#include "mct_d_gcc.h"<br>+<br> static void CalcEccDQSPos_D(struct MCTStatStruc *pMCTstat,<br> struct DCTStatStruc *pDCTstat, u16 like,<br> u8 scale, u8 ChipSel);<br>diff --git a/src/northbridge/amd/amdmct/mct/mctmtr_d.c b/src/northbridge/amd/amdmct/mct/mctmtr_d.c<br>index 0a157ed..ce5a60c 100644<br>--- a/src/northbridge/amd/amdmct/mct/mctmtr_d.c<br>+++ b/src/northbridge/amd/amdmct/mct/mctmtr_d.c<br>@@ -14,9 +14,11 @@<br> */<br> <br> #include <northbridge/amd/amdfam10/debug.h><br>-#include "mct_d.h"<br> #include <cpu/amd/mtrr.h><br> <br>+#include "mct_d.h"<br>+#include "mct_d_gcc.h"<br>+<br> static void SetMTRRrangeWB_D(u32 Base, u32 *pLimit, u32 *pMtrrAddr);<br> static void SetMTRRrange_D(u32 Base, u32 *pLimit, u32 *pMtrrAddr, u16 MtrrType);<br> <br>diff --git a/src/northbridge/amd/amdmct/mct/mctndi_d.c b/src/northbridge/amd/amdmct/mct/mctndi_d.c<br>index fe2bf9e..a95f1c9 100644<br>--- a/src/northbridge/amd/amdmct/mct/mctndi_d.c<br>+++ b/src/northbridge/amd/amdmct/mct/mctndi_d.c<br>@@ -15,7 +15,10 @@<br> */<br> <br> #include <northbridge/amd/amdfam10/debug.h><br>+<br> #include "mct_d.h"<br>+#include "mct_d_gcc.h"<br>+<br> <br> void InterleaveNodes_D(struct MCTStatStruc *pMCTstat,<br> struct DCTStatStruc *pDCTstatA)<br>diff --git a/src/northbridge/amd/amdmct/mct/mctpro_d.c b/src/northbridge/amd/amdmct/mct/mctpro_d.c<br>index 18d69b5..90f1a42 100644<br>--- a/src/northbridge/amd/amdmct/mct/mctpro_d.c<br>+++ b/src/northbridge/amd/amdmct/mct/mctpro_d.c<br>@@ -15,7 +15,10 @@<br> */<br> <br> #include <northbridge/amd/amdfam10/debug.h><br>+<br> #include "mct_d.h"<br>+#include "mct_d_gcc.h"<br>+<br> <br> void EarlySampleSupport_D(void)<br> {<br>diff --git a/src/northbridge/amd/amdmct/mct/mctsrc.c b/src/northbridge/amd/amdmct/mct/mctsrc.c<br>index c53b947..3a78620 100644<br>--- a/src/northbridge/amd/amdmct/mct/mctsrc.c<br>+++ b/src/northbridge/amd/amdmct/mct/mctsrc.c<br>@@ -15,9 +15,12 @@<br> */<br> <br> #include <northbridge/amd/amdfam10/debug.h><br>-#include "mct_d.h"<br> #include <cpu/x86/cr.h><br> <br>+#include "mct_d.h"<br>+#include "mct_d_gcc.h"<br>+<br>+<br> /******************************************************************************<br> Description: Receiver En and DQS Timing Training feature for DDR 2 MCT<br> ******************************************************************************/<br>diff --git a/src/northbridge/amd/amdmct/mct/mcttmrl.c b/src/northbridge/amd/amdmct/mct/mcttmrl.c<br>index 4c6d8e6..81ec5f9 100644<br>--- a/src/northbridge/amd/amdmct/mct/mcttmrl.c<br>+++ b/src/northbridge/amd/amdmct/mct/mcttmrl.c<br>@@ -13,9 +13,11 @@<br> * GNU General Public License for more details.<br> */<br> <br>-#include "mct_d.h"<br> #include <cpu/x86/cr.h><br> <br>+#include "mct_d.h"<br>+#include "mct_d_gcc.h"<br>+<br> /*<br> * Description: Max Read Latency Training feature for DDR 2 MCT<br> */<br></pre><p>To view, visit <a href="https://review.coreboot.org/20972">change 20972</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/20972"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I454eb9f00c8ffebd7a48bf9cb65d012b3fc335f2 </div>
<div style="display:none"> Gerrit-Change-Number: 20972 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Arthur Heymans <arthur@aheymans.xyz> </div>