[coreboot-gerrit] Change in coreboot[master]: soc/amd/stoneyridge: Add postcar stage
Marshall Dawson (Code Review)
gerrit at coreboot.org
Sat Aug 12 00:44:21 CEST 2017
Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/20966
Change subject: soc/amd/stoneyridge: Add postcar stage
......................................................................
soc/amd/stoneyridge: Add postcar stage
Insert a postcar stage for Stoney Ridge and move romstage's CAR
teardown there.
The AMD cache-as-ram teardown procedure currently uses a wbinvd
instruction to send CAR contents to DRAM backing. This allows
preserving stack contents and CAR globals after the teardown
happens, but likely results in memory corruption during S3 resume.
Due to the current base of the DCACHE region, reverting to an
invd instruction will break the detection mechanism for CAR
migrated variables. Using postcar avoids this problem.
The current behavior of AGESA is to set up all cores' MTRRs during
the AmdInitPost() entry point. This implementation preloads the
postcar frame with those settings to avoid them being erased by
the postcar _start.
The change also moves AmdInitEnv(), which needs to follow CAR
teardown, from romstage to the earliest opportunity in ramstage.
Change-Id: I1045446655b81b806d75903d75288ab17b5e77d1
Signed-off-by: Marshall Dawson <marshalldawson3rd at gmail.com>
---
M src/soc/amd/common/block/cpu/Makefile.inc
M src/soc/amd/stoneyridge/Kconfig
M src/soc/amd/stoneyridge/Makefile.inc
M src/soc/amd/stoneyridge/chip.c
M src/soc/amd/stoneyridge/include/soc/northbridge.h
M src/soc/amd/stoneyridge/romstage.c
M src/vendorcode/amd/pi/Makefile.inc
7 files changed, 49 insertions(+), 14 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/20966/1
diff --git a/src/soc/amd/common/block/cpu/Makefile.inc b/src/soc/amd/common/block/cpu/Makefile.inc
index 8e6972e..ecc9afb 100644
--- a/src/soc/amd/common/block/cpu/Makefile.inc
+++ b/src/soc/amd/common/block/cpu/Makefile.inc
@@ -1,2 +1,3 @@
bootblock-$(CONFIG_SOC_AMD_COMMON_BLOCK_CAR) += car/cache_as_ram.S
+postcar-$(CONFIG_SOC_AMD_COMMON_BLOCK_CAR) += car/exit_car.S
romstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_CAR) += car/exit_car.S
diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig
index 0425beb..4a7f6c7 100644
--- a/src/soc/amd/stoneyridge/Kconfig
+++ b/src/soc/amd/stoneyridge/Kconfig
@@ -49,6 +49,10 @@
select SOC_AMD_COMMON_BLOCK_CAR
select C_ENVIRONMENT_BOOTBLOCK
select BOOTBLOCK_CONSOLE
+ select RELOCATABLE_MODULES
+ select RELOCATABLE_RAMSTAGE
+ select POSTCAR_STAGE
+ select POSTCAR_CONSOLE
config VBOOT
select AMDFW_OUTSIDE_CBFS
diff --git a/src/soc/amd/stoneyridge/Makefile.inc b/src/soc/amd/stoneyridge/Makefile.inc
index 30006b3..8c435e6 100644
--- a/src/soc/amd/stoneyridge/Makefile.inc
+++ b/src/soc/amd/stoneyridge/Makefile.inc
@@ -60,6 +60,9 @@
verstage-$(CONFIG_STONEYRIDGE_UART) += uart.c
verstage-y += tsc_freq.c
+postcar-$(CONFIG_STONEYRIDGE_UART) += uart.c
+postcar-y += ramtop.c
+
ramstage-y += chip.c
ramstage-$(CONFIG_USBDEBUG) += enable_usbdebug.c
ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c
diff --git a/src/soc/amd/stoneyridge/chip.c b/src/soc/amd/stoneyridge/chip.c
index 2af466b..b586af1 100644
--- a/src/soc/amd/stoneyridge/chip.c
+++ b/src/soc/amd/stoneyridge/chip.c
@@ -14,10 +14,13 @@
*/
#include <chip.h>
+#include <bootstate.h>
#include <cpu/amd/mtrr.h>
#include <cpu/cpu.h>
#include <device/device.h>
#include <device/pci.h>
+#include <agesawrapper.h>
+#include <agesawrapper_call.h>
#include <soc/hudson.h>
#include <soc/northbridge.h>
@@ -78,3 +81,11 @@
.init = &soc_init,
.final = &soc_final
};
+
+static void do_initenv(void *unused)
+{
+ post_code(0x46);
+ AGESAWRAPPER(amdinitenv);
+}
+
+BOOT_STATE_INIT_ENTRY(BS_PRE_DEVICE, BS_ON_ENTRY, do_initenv, NULL);
diff --git a/src/soc/amd/stoneyridge/include/soc/northbridge.h b/src/soc/amd/stoneyridge/include/soc/northbridge.h
index e082a9d..1509850 100644
--- a/src/soc/amd/stoneyridge/include/soc/northbridge.h
+++ b/src/soc/amd/stoneyridge/include/soc/northbridge.h
@@ -27,7 +27,4 @@
void fam15_finalize(void *chip_info);
void setup_uma_memory(void);
-/* todo: remove this when postcar stage is in place */
-asmlinkage void chipset_teardown_car(void);
-
#endif /* PI_STONEYRIDGE_NORTHBRIDGE_H */
diff --git a/src/soc/amd/stoneyridge/romstage.c b/src/soc/amd/stoneyridge/romstage.c
index 1380fb7..c3154c1 100644
--- a/src/soc/amd/stoneyridge/romstage.c
+++ b/src/soc/amd/stoneyridge/romstage.c
@@ -13,6 +13,9 @@
* GNU General Public License for more details.
*/
+#include <arch/cpu.h>
+#include <cpu/x86/msr.h>
+#include <cpu/x86/mtrr.h>
#include <cbmem.h>
#include <console/console.h>
#include <program_loading.h>
@@ -24,6 +27,9 @@
asmlinkage void car_stage_entry(void)
{
+ struct postcar_frame pcf;
+ int i;
+
console_init();
post_code(0x40);
@@ -35,18 +41,30 @@
post_code(0x42);
cbmem_initialize_empty();
- /*
- * This writes contents to DRAM backing before teardown.
- * todo: move CAR teardown to postcar implementation and
- * relocate amdinitenv to ramstage.
- */
- chipset_teardown_car();
-
post_code(0x43);
- AGESAWRAPPER(amdinitenv);
+ if (postcar_frame_init(&pcf, 1*KiB))
+ die("Unable to initialize postcar frame.\n");
- post_code(0x50);
- run_ramstage();
+ post_code(0x44);
+ /* AGESA has already set up MTRRs. Put into frame to preserve them. */
+ for (i = 0 ; i < 7 ; i++) {
+ msr_t base = rdmsr(MTRR_PHYS_BASE(i));
+ msr_t mask = rdmsr(MTRR_PHYS_MASK(i));
+ if (!(mask.lo & MTRR_PHYS_MASK_VALID))
+ continue;
- post_code(0x54); /* Should never see this post code. */
+ /*
+ * Note: Only ranges below 4GB are programmed to MTRRs by
+ * AGESA so the base.hi may be assumed = 0. The DRAM region
+ * above 4GB is automatically handled by setting the
+ * Tom2ForceMemTypeWB bit in in SYS_CFG.
+ */
+ postcar_frame_add_mtrr(&pcf, base.lo & ~0xfff,
+ ~(mask.lo & ~0xfff) + 1, base.lo & 0x7);
+ }
+
+ post_code(0x45);
+ run_postcar_phase(&pcf);
+
+ post_code(0x50); /* Should never see this post code. */
}
diff --git a/src/vendorcode/amd/pi/Makefile.inc b/src/vendorcode/amd/pi/Makefile.inc
index bcf078d..b1f658f 100644
--- a/src/vendorcode/amd/pi/Makefile.inc
+++ b/src/vendorcode/amd/pi/Makefile.inc
@@ -85,6 +85,7 @@
CC_bootblock := $(CC_bootblock) $(AGESA_INC) $(AGESA_CFLAGS)
CC_romstage := $(CC_romstage) $(AGESA_INC) $(AGESA_CFLAGS)
+CC_postcar := $(CC_postcar) $(AGESA_INC) $(AGESA_CFLAGS)
CC_ramstage := $(CC_ramstage) $(AGESA_INC) $(AGESA_CFLAGS)
CC_x86_32 := $(CC_x86_32) $(AGESA_INC) $(AGESA_CFLAGS)
CC_x86_64 := $(CC_x86_64) $(AGESA_INC) $(AGESA_CFLAGS)
--
To view, visit https://review.coreboot.org/20966
To unsubscribe, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I1045446655b81b806d75903d75288ab17b5e77d1
Gerrit-Change-Number: 20966
Gerrit-PatchSet: 1
Gerrit-Owner: Marshall Dawson <marshalldawson3rd at gmail.com>
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://mail.coreboot.org/pipermail/coreboot-gerrit/attachments/20170811/832e6fb6/attachment-0001.html>
More information about the coreboot-gerrit
mailing list