<p>Marshall Dawson has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/20966">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/amd/stoneyridge: Add postcar stage<br><br>Insert a postcar stage for Stoney Ridge and move romstage's CAR<br>teardown there.<br><br>The AMD cache-as-ram teardown procedure currently uses a wbinvd<br>instruction to send CAR contents to DRAM backing. This allows<br>preserving stack contents and CAR globals after the teardown<br>happens, but likely results in memory corruption during S3 resume.<br>Due to the current base of the DCACHE region, reverting to an<br>invd instruction will break the detection mechanism for CAR<br>migrated variables. Using postcar avoids this problem.<br><br>The current behavior of AGESA is to set up all cores' MTRRs during<br>the AmdInitPost() entry point. This implementation preloads the<br>postcar frame with those settings to avoid them being erased by<br>the postcar _start.<br><br>The change also moves AmdInitEnv(), which needs to follow CAR<br>teardown, from romstage to the earliest opportunity in ramstage.<br><br>Change-Id: I1045446655b81b806d75903d75288ab17b5e77d1<br>Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com><br>---<br>M src/soc/amd/common/block/cpu/Makefile.inc<br>M src/soc/amd/stoneyridge/Kconfig<br>M src/soc/amd/stoneyridge/Makefile.inc<br>M src/soc/amd/stoneyridge/chip.c<br>M src/soc/amd/stoneyridge/include/soc/northbridge.h<br>M src/soc/amd/stoneyridge/romstage.c<br>M src/vendorcode/amd/pi/Makefile.inc<br>7 files changed, 49 insertions(+), 14 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/20966/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/soc/amd/common/block/cpu/Makefile.inc b/src/soc/amd/common/block/cpu/Makefile.inc<br>index 8e6972e..ecc9afb 100644<br>--- a/src/soc/amd/common/block/cpu/Makefile.inc<br>+++ b/src/soc/amd/common/block/cpu/Makefile.inc<br>@@ -1,2 +1,3 @@<br> bootblock-$(CONFIG_SOC_AMD_COMMON_BLOCK_CAR) += car/cache_as_ram.S<br>+postcar-$(CONFIG_SOC_AMD_COMMON_BLOCK_CAR) += car/exit_car.S<br> romstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_CAR) += car/exit_car.S<br>diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig<br>index 0425beb..4a7f6c7 100644<br>--- a/src/soc/amd/stoneyridge/Kconfig<br>+++ b/src/soc/amd/stoneyridge/Kconfig<br>@@ -49,6 +49,10 @@<br> select SOC_AMD_COMMON_BLOCK_CAR<br> select C_ENVIRONMENT_BOOTBLOCK<br> select BOOTBLOCK_CONSOLE<br>+ select RELOCATABLE_MODULES<br>+ select RELOCATABLE_RAMSTAGE<br>+ select POSTCAR_STAGE<br>+ select POSTCAR_CONSOLE<br> <br> config VBOOT<br> select AMDFW_OUTSIDE_CBFS<br>diff --git a/src/soc/amd/stoneyridge/Makefile.inc b/src/soc/amd/stoneyridge/Makefile.inc<br>index 30006b3..8c435e6 100644<br>--- a/src/soc/amd/stoneyridge/Makefile.inc<br>+++ b/src/soc/amd/stoneyridge/Makefile.inc<br>@@ -60,6 +60,9 @@<br> verstage-$(CONFIG_STONEYRIDGE_UART) += uart.c<br> verstage-y += tsc_freq.c<br> <br>+postcar-$(CONFIG_STONEYRIDGE_UART) += uart.c<br>+postcar-y += ramtop.c<br>+<br> ramstage-y += chip.c<br> ramstage-$(CONFIG_USBDEBUG) += enable_usbdebug.c<br> ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c<br>diff --git a/src/soc/amd/stoneyridge/chip.c b/src/soc/amd/stoneyridge/chip.c<br>index 2af466b..b586af1 100644<br>--- a/src/soc/amd/stoneyridge/chip.c<br>+++ b/src/soc/amd/stoneyridge/chip.c<br>@@ -14,10 +14,13 @@<br> */<br> <br> #include <chip.h><br>+#include <bootstate.h><br> #include <cpu/amd/mtrr.h><br> #include <cpu/cpu.h><br> #include <device/device.h><br> #include <device/pci.h><br>+#include <agesawrapper.h><br>+#include <agesawrapper_call.h><br> #include <soc/hudson.h><br> #include <soc/northbridge.h><br> <br>@@ -78,3 +81,11 @@<br> .init = &soc_init,<br> .final = &soc_final<br> };<br>+<br>+static void do_initenv(void *unused)<br>+{<br>+ post_code(0x46);<br>+ AGESAWRAPPER(amdinitenv);<br>+}<br>+<br>+BOOT_STATE_INIT_ENTRY(BS_PRE_DEVICE, BS_ON_ENTRY, do_initenv, NULL);<br>diff --git a/src/soc/amd/stoneyridge/include/soc/northbridge.h b/src/soc/amd/stoneyridge/include/soc/northbridge.h<br>index e082a9d..1509850 100644<br>--- a/src/soc/amd/stoneyridge/include/soc/northbridge.h<br>+++ b/src/soc/amd/stoneyridge/include/soc/northbridge.h<br>@@ -27,7 +27,4 @@<br> void fam15_finalize(void *chip_info);<br> void setup_uma_memory(void);<br> <br>-/* todo: remove this when postcar stage is in place */<br>-asmlinkage void chipset_teardown_car(void);<br>-<br> #endif /* PI_STONEYRIDGE_NORTHBRIDGE_H */<br>diff --git a/src/soc/amd/stoneyridge/romstage.c b/src/soc/amd/stoneyridge/romstage.c<br>index 1380fb7..c3154c1 100644<br>--- a/src/soc/amd/stoneyridge/romstage.c<br>+++ b/src/soc/amd/stoneyridge/romstage.c<br>@@ -13,6 +13,9 @@<br> * GNU General Public License for more details.<br> */<br> <br>+#include <arch/cpu.h><br>+#include <cpu/x86/msr.h><br>+#include <cpu/x86/mtrr.h><br> #include <cbmem.h><br> #include <console/console.h><br> #include <program_loading.h><br>@@ -24,6 +27,9 @@<br> <br> asmlinkage void car_stage_entry(void)<br> {<br>+ struct postcar_frame pcf;<br>+ int i;<br>+<br> console_init();<br> <br> post_code(0x40);<br>@@ -35,18 +41,30 @@<br> post_code(0x42);<br> cbmem_initialize_empty();<br> <br>- /*<br>- * This writes contents to DRAM backing before teardown.<br>- * todo: move CAR teardown to postcar implementation and<br>- * relocate amdinitenv to ramstage.<br>- */<br>- chipset_teardown_car();<br>-<br> post_code(0x43);<br>- AGESAWRAPPER(amdinitenv);<br>+ if (postcar_frame_init(&pcf, 1*KiB))<br>+ die("Unable to initialize postcar frame.\n");<br> <br>- post_code(0x50);<br>- run_ramstage();<br>+ post_code(0x44);<br>+ /* AGESA has already set up MTRRs. Put into frame to preserve them. */<br>+ for (i = 0 ; i < 7 ; i++) {<br>+ msr_t base = rdmsr(MTRR_PHYS_BASE(i));<br>+ msr_t mask = rdmsr(MTRR_PHYS_MASK(i));<br>+ if (!(mask.lo & MTRR_PHYS_MASK_VALID))<br>+ continue;<br> <br>- post_code(0x54); /* Should never see this post code. */<br>+ /*<br>+ * Note: Only ranges below 4GB are programmed to MTRRs by<br>+ * AGESA so the base.hi may be assumed = 0. The DRAM region<br>+ * above 4GB is automatically handled by setting the<br>+ * Tom2ForceMemTypeWB bit in in SYS_CFG.<br>+ */<br>+ postcar_frame_add_mtrr(&pcf, base.lo & ~0xfff,<br>+ ~(mask.lo & ~0xfff) + 1, base.lo & 0x7);<br>+ }<br>+<br>+ post_code(0x45);<br>+ run_postcar_phase(&pcf);<br>+<br>+ post_code(0x50); /* Should never see this post code. */<br> }<br>diff --git a/src/vendorcode/amd/pi/Makefile.inc b/src/vendorcode/amd/pi/Makefile.inc<br>index bcf078d..b1f658f 100644<br>--- a/src/vendorcode/amd/pi/Makefile.inc<br>+++ b/src/vendorcode/amd/pi/Makefile.inc<br>@@ -85,6 +85,7 @@<br> <br> CC_bootblock := $(CC_bootblock) $(AGESA_INC) $(AGESA_CFLAGS)<br> CC_romstage := $(CC_romstage) $(AGESA_INC) $(AGESA_CFLAGS)<br>+CC_postcar := $(CC_postcar) $(AGESA_INC) $(AGESA_CFLAGS)<br> CC_ramstage := $(CC_ramstage) $(AGESA_INC) $(AGESA_CFLAGS)<br> CC_x86_32 := $(CC_x86_32) $(AGESA_INC) $(AGESA_CFLAGS)<br> CC_x86_64 := $(CC_x86_64) $(AGESA_INC) $(AGESA_CFLAGS)<br></pre><p>To view, visit <a href="https://review.coreboot.org/20966">change 20966</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/20966"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I1045446655b81b806d75903d75288ab17b5e77d1 </div>
<div style="display:none"> Gerrit-Change-Number: 20966 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Marshall Dawson <marshalldawson3rd@gmail.com> </div>