[coreboot-gerrit] Change in coreboot[master]: soc/intel/skylake: Configure FSP to skip ME MBP step

[Duncan Laurie (Code Review)]

Duncan Laurie has uploaded this change for review. ( https://review.coreboot.org/20951


Change subject: soc/intel/skylake: Configure FSP to skip ME MBP step
......................................................................

soc/intel/skylake: Configure FSP to skip ME MBP step

We do not need or use the Management Engine MBP HOB so that
step can be skipped when FSP initializes the ME.

BUG=b:64479422
TEST=boot with FSP debug enabled binary and ensure that the
output indicates this step is being skipped:
Skipping MBP data due to SkipMbpHob set!

Change-Id: I5ea22ec4b8b47fa17b1cf2bf562337bfaad5ec0d
Signed-off-by: Duncan Laurie <dlaurie at google.com>
---
M src/soc/intel/skylake/romstage/romstage_fsp20.c
1 file changed, 3 insertions(+), 0 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/20951/1

diff --git a/src/soc/intel/skylake/romstage/romstage_fsp20.c b/src/soc/intel/skylake/romstage/romstage_fsp20.c
index e439d734..c43bdc3 100644
--- a/src/soc/intel/skylake/romstage/romstage_fsp20.c
+++ b/src/soc/intel/skylake/romstage/romstage_fsp20.c
@@ -222,6 +222,9 @@
 
 	soc_memory_init_params(m_cfg, config);
 
+	/* Skip creating Management Engine MBP HOB */
+	m_t_cfg->SkipMbpHob = 0x01;
+
 	/* Enable DMI Virtual Channel for ME */
 	m_t_cfg->DmiVcm = 0x01;
 

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I5ea22ec4b8b47fa17b1cf2bf562337bfaad5ec0d
Gerrit-Change-Number: 20951
Gerrit-PatchSet: 1
Gerrit-Owner: Duncan Laurie <dlaurie at chromium.org>
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