[coreboot-gerrit] Change in coreboot[master]: stoneyridge: Fix CPU ASL \_PR table

[Marc Jones (Code Review)]

Marc Jones has uploaded this change for review. ( https://review.coreboot.org/20910


Change subject: stoneyridge: Fix CPU ASL \_PR table
......................................................................

stoneyridge: Fix CPU ASL \_PR table

The PMIO region was moved, but not updated in the ASL. Change to
generate \_PR table runtime and to report the correct PMIO region.

Fix on Kahlee, where the EC overlaps the region:
[    0.802721] cros_ec_lpcs GOOG0004:00: couldn't reserve region0
[    0.807446] cros_ec_lpcs: probe of GOOG0004:00 failed with error -16

BUG=b:63902389
BRANCH=none
TEST=Cros_ec_lps can reserve the region. ACPI tables are correct.

Change-Id: I870f810cc5d2edc0b842478cde5b3c164ed3b47f
Signed-off-by: Marc Jones <marcj303 at gmail.com>
---
M src/soc/amd/stoneyridge/acpi.c
M src/soc/amd/stoneyridge/acpi/cpu.asl
M src/soc/amd/stoneyridge/chip.c
3 files changed, 36 insertions(+), 59 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/20910/1

diff --git a/src/soc/amd/stoneyridge/acpi.c b/src/soc/amd/stoneyridge/acpi.c
index 54af59b..327faef 100644
--- a/src/soc/amd/stoneyridge/acpi.c
+++ b/src/soc/amd/stoneyridge/acpi.c
@@ -26,6 +26,7 @@
 #include <arch/ioapic.h>
 #include <cbmem.h>
 #include <device/device.h>
+#include <device/pci.h>
 #include <soc/acpi.h>
 #include <soc/hudson.h>
 #include <soc/nvs.h>
@@ -231,6 +232,31 @@
 	header->checksum = acpi_checksum((void *)fadt, sizeof(acpi_fadt_t));
 }
 
+void generate_cpu_entries(device_t device)
+{
+	int cores, cpu, plen = 6;
+	u32 pcontrol_blk = ACPI_GPE0_BLK;
+	device_t cdb_dev;
+
+	/* Stoney Ridge is single node, just report # of cores */
+	cdb_dev = dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB, 5));
+	cores = (pci_read_config32(cdb_dev, 0x84) & 0xff) + 1;
+
+	printk(BIOS_DEBUG, "ACPI \\_PR report %d core(s)\n", cores);
+
+	for (cpu = 0; cpu < cores; cpu++) {
+		if (cpu > 0) {
+			pcontrol_blk = 0;
+			plen = 0;
+		}
+
+		/* Generate processor \_PR.CPUx */
+		acpigen_write_processor(cpu, pcontrol_blk, plen);
+
+		acpigen_pop_len();
+	}
+}
+
 unsigned long southbridge_write_acpi_tables(device_t device,
 		unsigned long current,
 		struct acpi_rsdp *rsdp)
diff --git a/src/soc/amd/stoneyridge/acpi/cpu.asl b/src/soc/amd/stoneyridge/acpi/cpu.asl
index 32dad76..9da1550 100644
--- a/src/soc/amd/stoneyridge/acpi/cpu.asl
+++ b/src/soc/amd/stoneyridge/acpi/cpu.asl
@@ -21,62 +21,12 @@
 /*
  * Processor Object
  */
-Scope (\_PR) {		/* define processor scope */
-	Processor(
-		P000,		/* name space name */
-		0,		/* Unique number for this processor */
-		0x810,		/* PBLK system I/O address !hardcoded! */
-		0x06		/* PBLKLEN for boot processor */
-		) {
-	}
-
-	Processor(
-		P001,		/* name space name */
-		1,		/* Unique number for this processor */
-		0x0810,		/* PBLK system I/O address !hardcoded! */
-		0x06		/* PBLKLEN for boot processor */
-		) {
-	}
-	Processor(
-		P002,		/* name space name */
-		2,		/* Unique number for this processor */
-		0x0810,		/* PBLK system I/O address !hardcoded! */
-		0x06		/* PBLKLEN for boot processor */
-		) {
-	}
-	Processor(
-		P003,		/* name space name */
-		3,		/* Unique number for this processor */
-		0x0810,		/* PBLK system I/O address !hardcoded! */
-		0x06		/* PBLKLEN for boot processor */
-		) {
-	}
-	Processor(
-		P004,		/* name space name */
-		4,		/* Unique number for this processor */
-		0x0810,		/* PBLK system I/O address !hardcoded! */
-		0x06		/* PBLKLEN for boot processor */
-		) {
-	}
-	Processor(
-		P005,		/* name space name */
-		5,		/* Unique number for this processor */
-		0x0810,		/* PBLK system I/O address !hardcoded! */
-		0x06		/* PBLKLEN for boot processor */
-		) {
-	}
-	Processor(
-		P006,		/* name space name */
-		6,		/* Unique number for this processor */
-		0x0810,		/* PBLK system I/O address !hardcoded! */
-		0x06		/* PBLKLEN for boot processor */
-		) {
-	}
-	Processor(
-		P007,		/* name space name */
-		7,		/* Unique number for this processor */
-		0x0810,		/* PBLK system I/O address !hardcoded! */
-		0x06		/* PBLKLEN for boot processor */
-		) {
-	}
-} /* End _PR scope */
+/* These devices are created at runtime */
+External (\_PR.CP00, DeviceObj)
+External (\_PR.CP01, DeviceObj)
+External (\_PR.CP02, DeviceObj)
+External (\_PR.CP03, DeviceObj)
+External (\_PR.CP04, DeviceObj)
+External (\_PR.CP05, DeviceObj)
+External (\_PR.CP06, DeviceObj)
+External (\_PR.CP07, DeviceObj)
diff --git a/src/soc/amd/stoneyridge/chip.c b/src/soc/amd/stoneyridge/chip.c
index 2af466b..487201b 100644
--- a/src/soc/amd/stoneyridge/chip.c
+++ b/src/soc/amd/stoneyridge/chip.c
@@ -32,6 +32,7 @@
 	.enable_resources = DEVICE_NOOP,
 	.init		  = &cpu_bus_init,
 	.scan_bus	  = cpu_bus_scan,
+	.acpi_fill_ssdt_generator = generate_cpu_entries,
 };
 
 struct device_operations pci_domain_ops = {

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I870f810cc5d2edc0b842478cde5b3c164ed3b47f
Gerrit-Change-Number: 20910
Gerrit-PatchSet: 1
Gerrit-Owner: Marc Jones <marc at marcjonesconsulting.com>
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