<p>Marc Jones has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/20910">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">stoneyridge: Fix CPU ASL \_PR table<br><br>The PMIO region was moved, but not updated in the ASL. Change to<br>generate \_PR table runtime and to report the correct PMIO region.<br><br>Fix on Kahlee, where the EC overlaps the region:<br>[ 0.802721] cros_ec_lpcs GOOG0004:00: couldn't reserve region0<br>[ 0.807446] cros_ec_lpcs: probe of GOOG0004:00 failed with error -16<br><br>BUG=b:63902389<br>BRANCH=none<br>TEST=Cros_ec_lps can reserve the region. ACPI tables are correct.<br><br>Change-Id: I870f810cc5d2edc0b842478cde5b3c164ed3b47f<br>Signed-off-by: Marc Jones <marcj303@gmail.com><br>---<br>M src/soc/amd/stoneyridge/acpi.c<br>M src/soc/amd/stoneyridge/acpi/cpu.asl<br>M src/soc/amd/stoneyridge/chip.c<br>3 files changed, 36 insertions(+), 59 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/20910/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/soc/amd/stoneyridge/acpi.c b/src/soc/amd/stoneyridge/acpi.c<br>index 54af59b..327faef 100644<br>--- a/src/soc/amd/stoneyridge/acpi.c<br>+++ b/src/soc/amd/stoneyridge/acpi.c<br>@@ -26,6 +26,7 @@<br> #include <arch/ioapic.h><br> #include <cbmem.h><br> #include <device/device.h><br>+#include <device/pci.h><br> #include <soc/acpi.h><br> #include <soc/hudson.h><br> #include <soc/nvs.h><br>@@ -231,6 +232,31 @@<br> header->checksum = acpi_checksum((void *)fadt, sizeof(acpi_fadt_t));<br> }<br> <br>+void generate_cpu_entries(device_t device)<br>+{<br>+ int cores, cpu, plen = 6;<br>+ u32 pcontrol_blk = ACPI_GPE0_BLK;<br>+ device_t cdb_dev;<br>+<br>+ /* Stoney Ridge is single node, just report # of cores */<br>+ cdb_dev = dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB, 5));<br>+ cores = (pci_read_config32(cdb_dev, 0x84) & 0xff) + 1;<br>+<br>+ printk(BIOS_DEBUG, "ACPI \\_PR report %d core(s)\n", cores);<br>+<br>+ for (cpu = 0; cpu < cores; cpu++) {<br>+ if (cpu > 0) {<br>+ pcontrol_blk = 0;<br>+ plen = 0;<br>+ }<br>+<br>+ /* Generate processor \_PR.CPUx */<br>+ acpigen_write_processor(cpu, pcontrol_blk, plen);<br>+<br>+ acpigen_pop_len();<br>+ }<br>+}<br>+<br> unsigned long southbridge_write_acpi_tables(device_t device,<br> unsigned long current,<br> struct acpi_rsdp *rsdp)<br>diff --git a/src/soc/amd/stoneyridge/acpi/cpu.asl b/src/soc/amd/stoneyridge/acpi/cpu.asl<br>index 32dad76..9da1550 100644<br>--- a/src/soc/amd/stoneyridge/acpi/cpu.asl<br>+++ b/src/soc/amd/stoneyridge/acpi/cpu.asl<br>@@ -21,62 +21,12 @@<br> /*<br> * Processor Object<br> */<br>-Scope (\_PR) { /* define processor scope */<br>- Processor(<br>- P000, /* name space name */<br>- 0, /* Unique number for this processor */<br>- 0x810, /* PBLK system I/O address !hardcoded! */<br>- 0x06 /* PBLKLEN for boot processor */<br>- ) {<br>- }<br>-<br>- Processor(<br>- P001, /* name space name */<br>- 1, /* Unique number for this processor */<br>- 0x0810, /* PBLK system I/O address !hardcoded! */<br>- 0x06 /* PBLKLEN for boot processor */<br>- ) {<br>- }<br>- Processor(<br>- P002, /* name space name */<br>- 2, /* Unique number for this processor */<br>- 0x0810, /* PBLK system I/O address !hardcoded! */<br>- 0x06 /* PBLKLEN for boot processor */<br>- ) {<br>- }<br>- Processor(<br>- P003, /* name space name */<br>- 3, /* Unique number for this processor */<br>- 0x0810, /* PBLK system I/O address !hardcoded! */<br>- 0x06 /* PBLKLEN for boot processor */<br>- ) {<br>- }<br>- Processor(<br>- P004, /* name space name */<br>- 4, /* Unique number for this processor */<br>- 0x0810, /* PBLK system I/O address !hardcoded! */<br>- 0x06 /* PBLKLEN for boot processor */<br>- ) {<br>- }<br>- Processor(<br>- P005, /* name space name */<br>- 5, /* Unique number for this processor */<br>- 0x0810, /* PBLK system I/O address !hardcoded! */<br>- 0x06 /* PBLKLEN for boot processor */<br>- ) {<br>- }<br>- Processor(<br>- P006, /* name space name */<br>- 6, /* Unique number for this processor */<br>- 0x0810, /* PBLK system I/O address !hardcoded! */<br>- 0x06 /* PBLKLEN for boot processor */<br>- ) {<br>- }<br>- Processor(<br>- P007, /* name space name */<br>- 7, /* Unique number for this processor */<br>- 0x0810, /* PBLK system I/O address !hardcoded! */<br>- 0x06 /* PBLKLEN for boot processor */<br>- ) {<br>- }<br>-} /* End _PR scope */<br>+/* These devices are created at runtime */<br>+External (\_PR.CP00, DeviceObj)<br>+External (\_PR.CP01, DeviceObj)<br>+External (\_PR.CP02, DeviceObj)<br>+External (\_PR.CP03, DeviceObj)<br>+External (\_PR.CP04, DeviceObj)<br>+External (\_PR.CP05, DeviceObj)<br>+External (\_PR.CP06, DeviceObj)<br>+External (\_PR.CP07, DeviceObj)<br>diff --git a/src/soc/amd/stoneyridge/chip.c b/src/soc/amd/stoneyridge/chip.c<br>index 2af466b..487201b 100644<br>--- a/src/soc/amd/stoneyridge/chip.c<br>+++ b/src/soc/amd/stoneyridge/chip.c<br>@@ -32,6 +32,7 @@<br> .enable_resources = DEVICE_NOOP,<br> .init = &cpu_bus_init,<br> .scan_bus = cpu_bus_scan,<br>+ .acpi_fill_ssdt_generator = generate_cpu_entries,<br> };<br> <br> struct device_operations pci_domain_ops = {<br></pre><p>To view, visit <a href="https://review.coreboot.org/20910">change 20910</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/20910"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I870f810cc5d2edc0b842478cde5b3c164ed3b47f </div>
<div style="display:none"> Gerrit-Change-Number: 20910 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Marc Jones <marc@marcjonesconsulting.com> </div>