[coreboot-gerrit] Change in coreboot[master]: nb/intel/sandybridge/raminit: Add Kconfig option for fuses

Patrick Rudolph (Code Review) gerrit at coreboot.org
Tue Aug 8 13:52:05 CEST 2017


Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/20907


Change subject: nb/intel/sandybridge/raminit: Add Kconfig option for fuses
......................................................................

nb/intel/sandybridge/raminit: Add Kconfig option for fuses

Add a new Kconfig option to ignore memory fuses that limit the
maximum DRAM frequency to be used. The option is disabled by
default and should only enabled by experienced users as it
might decrease system stability or prevent a successful RAM
training.

Remove conflicting devicetree settings.

Change-Id: I35dd78a02bcaafce8ba522d253c795d7835bacae
Signed-off-by: Patrick Rudolph <siro at das-labor.org>
---
M src/mainboard/lenovo/l520/devicetree.cb
M src/mainboard/lenovo/t420/devicetree.cb
M src/mainboard/lenovo/t420s/devicetree.cb
M src/mainboard/lenovo/t430/devicetree.cb
M src/mainboard/lenovo/t430s/devicetree.cb
M src/mainboard/lenovo/t520/devicetree.cb
M src/mainboard/lenovo/t530/devicetree.cb
M src/mainboard/lenovo/x1_carbon_gen1/devicetree.cb
M src/mainboard/lenovo/x220/devicetree.cb
M src/mainboard/lenovo/x230/devicetree.cb
M src/northbridge/intel/sandybridge/Kconfig
M src/northbridge/intel/sandybridge/raminit_common.c
12 files changed, 15 insertions(+), 30 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/20907/1

diff --git a/src/mainboard/lenovo/l520/devicetree.cb b/src/mainboard/lenovo/l520/devicetree.cb
index 542b06a..3e1f308 100644
--- a/src/mainboard/lenovo/l520/devicetree.cb
+++ b/src/mainboard/lenovo/l520/devicetree.cb
@@ -15,9 +15,6 @@
 	register "gpu_panel_power_up_delay" = "0"
 	register "gpu_pch_backlight" = "0x00000000"
 
-	# Override fuse bits that hard-code the value to 666 Mhz
-	register "max_mem_clock_mhz" = "933"
-
 	device cpu_cluster 0x0 on
 		chip cpu/intel/socket_rPGA989
 			device lapic 0x0 on
diff --git a/src/mainboard/lenovo/t420/devicetree.cb b/src/mainboard/lenovo/t420/devicetree.cb
index deb62b7..4c90a5e 100644
--- a/src/mainboard/lenovo/t420/devicetree.cb
+++ b/src/mainboard/lenovo/t420/devicetree.cb
@@ -18,9 +18,6 @@
 	register "gpu_cpu_backlight" = "0x1155"
 	register "gpu_pch_backlight" = "0x06100610"
 
-	# Override fuse bits that hard-code the value to 666 Mhz
-	register "max_mem_clock_mhz" = "933"
-
 	device cpu_cluster 0 on
 		chip cpu/intel/socket_rPGA988B
 			device lapic 0 on end
diff --git a/src/mainboard/lenovo/t420s/devicetree.cb b/src/mainboard/lenovo/t420s/devicetree.cb
index 3224322..655d39c 100644
--- a/src/mainboard/lenovo/t420s/devicetree.cb
+++ b/src/mainboard/lenovo/t420s/devicetree.cb
@@ -17,9 +17,6 @@
 	register "gpu_cpu_backlight" = "0x1155"
 	register "gpu_pch_backlight" = "0x06100610"
 
-	# Override fuse bits that hard-code the value to 666 Mhz
-	register "max_mem_clock_mhz" = "933"
-
 	device cpu_cluster 0 on
 		chip cpu/intel/socket_rPGA988B
 			device lapic 0 on end
diff --git a/src/mainboard/lenovo/t430/devicetree.cb b/src/mainboard/lenovo/t430/devicetree.cb
index 0a121b7..cc2d43f 100644
--- a/src/mainboard/lenovo/t430/devicetree.cb
+++ b/src/mainboard/lenovo/t430/devicetree.cb
@@ -34,9 +34,6 @@
 		end
 	end
 
-	# Override fuse bits that hard-code the value to 666 Mhz
-	register "max_mem_clock_mhz" = "933"
-
 	device domain 0x0 on
 		chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
 			register "c2_latency" = "0x0065"
diff --git a/src/mainboard/lenovo/t430s/devicetree.cb b/src/mainboard/lenovo/t430s/devicetree.cb
index ccee86a..6846879 100644
--- a/src/mainboard/lenovo/t430s/devicetree.cb
+++ b/src/mainboard/lenovo/t430s/devicetree.cb
@@ -17,9 +17,6 @@
 	register "gpu_cpu_backlight" = "0x1155"
 	register "gpu_pch_backlight" = "0x11551155"
 
-	# Override fuse bits that hard-code the value to 666 Mhz
-	register "max_mem_clock_mhz" = "933"
-
 	device cpu_cluster 0 on
 		chip cpu/intel/socket_rPGA989
 			device lapic 0 on end
diff --git a/src/mainboard/lenovo/t520/devicetree.cb b/src/mainboard/lenovo/t520/devicetree.cb
index 0065799..55f838a 100644
--- a/src/mainboard/lenovo/t520/devicetree.cb
+++ b/src/mainboard/lenovo/t520/devicetree.cb
@@ -18,9 +18,6 @@
 	register "gpu_cpu_backlight" = "0x1155"
 	register "gpu_pch_backlight" = "0x06100610"
 
-	# Override fuse bits that hard-code the value to 666 Mhz
-	register "max_mem_clock_mhz" = "933"
-
 	device cpu_cluster 0 on
 		chip cpu/intel/socket_rPGA988B
 			device lapic 0 on end
diff --git a/src/mainboard/lenovo/t530/devicetree.cb b/src/mainboard/lenovo/t530/devicetree.cb
index 2047a78..9f494b9 100644
--- a/src/mainboard/lenovo/t530/devicetree.cb
+++ b/src/mainboard/lenovo/t530/devicetree.cb
@@ -18,9 +18,6 @@
 	register "gpu_cpu_backlight" = "0x1155"
 	register "gpu_pch_backlight" = "0x11551155"
 
-	# Override fuse bits that hard-code the value to 666 Mhz
-	register "max_mem_clock_mhz" = "933"
-
 	device cpu_cluster 0 on
 		chip cpu/intel/socket_rPGA989
 			device lapic 0 on end
diff --git a/src/mainboard/lenovo/x1_carbon_gen1/devicetree.cb b/src/mainboard/lenovo/x1_carbon_gen1/devicetree.cb
index ce74d3f..e76f68a 100644
--- a/src/mainboard/lenovo/x1_carbon_gen1/devicetree.cb
+++ b/src/mainboard/lenovo/x1_carbon_gen1/devicetree.cb
@@ -15,9 +15,6 @@
 	register "gpu_panel_power_up_delay" = "300"
 	register "gpu_pch_backlight" = "0x11551155"
 
-	# Override fuse bits that hard-code the value to 666 Mhz
-	register "max_mem_clock_mhz" = "933"
-
 	device cpu_cluster 0 on
 		chip cpu/intel/socket_rPGA989
 			device lapic 0 on end
diff --git a/src/mainboard/lenovo/x220/devicetree.cb b/src/mainboard/lenovo/x220/devicetree.cb
index 62ad3b0..2bac65d 100644
--- a/src/mainboard/lenovo/x220/devicetree.cb
+++ b/src/mainboard/lenovo/x220/devicetree.cb
@@ -18,9 +18,6 @@
 	register "gpu_cpu_backlight" = "0x1155"
 	register "gpu_pch_backlight" = "0x06100610"
 
-	# Override fuse bits that hard-code the value to 666 Mhz
-	register "max_mem_clock_mhz" = "933"
-
 	device cpu_cluster 0 on
 		chip cpu/intel/socket_rPGA989
 			device lapic 0 on end
diff --git a/src/mainboard/lenovo/x230/devicetree.cb b/src/mainboard/lenovo/x230/devicetree.cb
index a1b0662..7a96a77 100644
--- a/src/mainboard/lenovo/x230/devicetree.cb
+++ b/src/mainboard/lenovo/x230/devicetree.cb
@@ -18,9 +18,6 @@
 	register "gpu_cpu_backlight" = "0x1155"
 	register "gpu_pch_backlight" = "0x11551155"
 
-	# Override fuse bits that hard-code the value to 666 Mhz
-	register "max_mem_clock_mhz" = "933"
-
 	device cpu_cluster 0 on
 		chip cpu/intel/socket_rPGA989
 			device lapic 0 on end
diff --git a/src/northbridge/intel/sandybridge/Kconfig b/src/northbridge/intel/sandybridge/Kconfig
index ae5ddfc..5a7ec46 100644
--- a/src/northbridge/intel/sandybridge/Kconfig
+++ b/src/northbridge/intel/sandybridge/Kconfig
@@ -44,6 +44,18 @@
 	  Select if you want to use coreboot implementation of raminit rather than
 	  System Agent/MRC.bin. You should answer Y.
 
+config NATIVE_RAMINIT_IGNORE_MAX_MEM_FUSES
+	bool "Ignore vendor programmed fuses that limit max. DRAM frequency"
+	default n
+	depends on USE_NATIVE_RAMINIT
+	help
+	  Ignore the mainboard's vendor programmed fuses that might limit the
+	  maximum DRAM frequency. By selecting this option the fuses will be
+	  ignored and the only limits on DRAM frequency are set by RAM's SPD and
+	  hard fuses in southbridge's clockgen.
+	  Disabled by default as it might causes system instability.
+	  Handle with care!
+
 config CBFS_SIZE
 	hex
 	default 0x100000
diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c
index c6ff551..3e69f4d 100644
--- a/src/northbridge/intel/sandybridge/raminit_common.c
+++ b/src/northbridge/intel/sandybridge/raminit_common.c
@@ -402,6 +402,9 @@
 
 	/* If this is zero, it just means devicetree.cb didn't set it */
 	if (!cfg || cfg->max_mem_clock_mhz == 0) {
+		if (IS_ENABLED(CONFIG_NATIVE_RAMINIT_IGNORE_MAX_MEM_FUSES))
+			return TCK_1333MHZ;
+
 		rev = pci_read_config8(PCI_DEV(0, 0, 0), PCI_DEVICE_ID);
 
 		if ((rev & BASE_REV_MASK) == BASE_REV_SNB) {

-- 
To view, visit https://review.coreboot.org/20907
To unsubscribe, visit https://review.coreboot.org/settings

Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I35dd78a02bcaafce8ba522d253c795d7835bacae
Gerrit-Change-Number: 20907
Gerrit-PatchSet: 1
Gerrit-Owner: Patrick Rudolph <siro at das-labor.org>
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://mail.coreboot.org/pipermail/coreboot-gerrit/attachments/20170808/7aad9878/attachment.html>


More information about the coreboot-gerrit mailing list